A New Low-Power Architecture Design for Distributed Arithmetic Unit in FIR Filter Implementation. - Seyedeh Fatemeh Ghamkhari; Mohammad Bagher Ghaznavi Ghoushchi (Circuits Syst. Signal Process., 2014)

Design and Implementation of Reconfigurable Integrated FPGA-based PSK Demodulator. - Seyedeh Fatemeh Ghamkhari; Shokrollah Karimian (IST, 2020)

A New Low Power Schema for Stream Processors Front-End with Power-Aware DA-Based FIR Filters by Investigation of Image Transitions Sparsity. - Seyedeh Fatemeh Ghamkhari; Mohammad Bagher Ghaznavi Ghoushchi (Circuits Syst. Signal Process., 2021)

A power-performance partitioning approach for low-power DA-based FIR filter design with emphasis on datapath and controller. - Seyedeh Fatemeh Ghamkhari; Mohammad Bagher Ghaznavi Ghoushchi (Int. J. Circuit Theory Appl., 2022)

AMPS: An Automated Mesochronous Pipeline Scheduler and Design Space Explorer for High Performance Digital Circuits. - Fateme Sadat Ayatollahi; M. B. Ghaznavi-Ghoushchi; Naser Mohammadzadeh; Seyedeh Fatemeh Ghamkhari (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)