Synthesis of resonant clock networks supporting dynamic voltage / frequency scaling. - Seyong Ahn; Minseok Kang; Marios C. Papaefthymiou; Taewhan Kim 001 (ASP-DAC, 2015)

Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency Scaling. - Seyong Ahn; Minseok Kang; Marios C. Papaefthymiou; Taewhan Kim 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Cohesive techniques for cell layout optimization supporting 2D metal-1 routing completion. - Kyeongrok Jo; Seyong Ahn; Taewhan Kim 001; Kyu-Myung Choi (ASP-DAC, 2018)

Design Rule Evaluation Framework Using Automatic Cell Layout Generator for Design Technology Co-Optimization. - Kyeongrok Jo; Seyong Ahn; Jungho Do; Taejoong Song; Taewhan Kim 001; Kyu-Myung Choi (IEEE Trans. Very Large Scale Integr. Syst., 2019)