A New Partitioning Strategy Based on Supermodular Functions. - Sachin B. Patkar; Shabbir H. Batterywala; M. Chandramouli; H. Narayanan (VLSI Design, 1997)

Efficient DC Analysis of RVJ Circuits for Moment and Derivative Commutations of Interconnect Networks. - Shabbir H. Batterywala; H. Narayanan (VLSI Design, 1999)

Spectral Algorithm To Compute And Synthesize Reduced Order Passive Models For Arbitrary Rc Multiports. - Shabbir H. Batterywala; H. Narayanan (VLSI Design, 2001)

Track assignment: a desirable intermediate step between global routing and detailed routing. - Shabbir H. Batterywala; Narendra V. Shenoy; William Nicholls; Hai Zhou 001 (ICCAD, 2002)

A Method to Estimate Slew and Delay in Coupled Digital Circuits. - Shabbir H. Batterywala; Narendra V. Shenoy (VLSI Design, 2003)

Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables. - Shabbir H. Batterywala; Narendra V. Shenoy (VLSI Design, 2004)

Variance Reduction in Monte Carlo Capacitance Extraction. - Shabbir H. Batterywala; Madhav P. Desai (VLSI Design, 2005)

MoM - A Process Variation Aware Statistical Capacitance Extractor. - Rohit Ananthakrishna; Shabbir H. Batterywala (VLSI Design, 2006)

A Statistical Method for Fast and Accurate Capacitance Extraction in the Presence of Floating Dummy Fills. - Shabbir H. Batterywala; Rohit Ananthakrishna; Yansheng Luo; Alex Gyure (VLSI Design, 2006)

A 3-dimensional FEM Based Resistance Extraction. - Subramanian Rajagopalan; Shabbir H. Batterywala (VLSI Design, 2007)

Impact of Modern Process Technologies on the Electrical Parameters of Interconnects. - Debjit Sinha; Jianfeng Luo 001; Subramanian Rajagopalan; Shabbir H. Batterywala; Narendra V. Shenoy; Hai Zhou 001 (VLSI Design, 2007)

Cell Swapping Based Migration Methodology for Analog and Custom Layouts. - Shabbir H. Batterywala; Sambuddha Bhattacharya; Subramanian Rajagopalan; Hi-Keung Tony Ma; Narendra V. Shenoy (ISQED, 2008)

On Efficient and Robust Constraint Generation for Practical Layout Legalization. - Sambuddha Bhattacharya; Shabbir H. Batterywala; Subramanian Rajagopalan; Hi-Keung Tony Ma; Narendra V. Shenoy (ISQED, 2008)

Efficient Analog/RF Layout Closure with Compaction Based Legalization. - Subramanian Rajagopalan; Sambuddha Bhattacharya; Shabbir H. Batterywala (VLSI Design, 2009)

Automatic design rule correction in presence of multiple grids and track patterns. - Nitin Salodkar; Subramanian Rajagopalan; Sambuddha Bhattacharya; Shabbir H. Batterywala (DAC, 2013)

Fixing Double Patterning violations with look-ahead. - Sambuddha Bhattacharya; Subramanian Rajagopalan; Shabbir H. Batterywala (ASP-DAC, 2014)

2SAT Based Infeasibility Resolution during Design Rule Correction on Layouts with Multiple Grids. - Nitin Salodkar; Subramanian Rajagopalan; Sambuddha Bhattacharya; Shabbir H. Batterywala (VLSID, 2015)