A Reduced-sp- ( hbox {D3L}_{ mathrm{sum}} ) Adder-Based High Frequency (4 times 4 ) Bit Multiplier Using Dadda Algorithm. - Zain Shabbir; Anas Razzaq Ghumman; Shabbir Majeed Chaudhry (Circuits Syst. Signal Process., 2016)

A 15-Bit 85 MS/s Hybrid Flash-SAR ADC in 90-nm CMOS. - Anas Razzaq Ghumman; Shabbir Majeed Chaudhry (Circuits Syst. Signal Process., 2018)

Design of a Feedback Loop Circuit for Quadrature Error Correction in 90-nm CMOS. - Muhammad Haseeb; Muhammad Usman; Shabbir Majeed Chaudhry (FIT, 2019)

Design of an Improved Low-Power and High-Speed Booth Multiplier. - Ahsan Rafiq; Shabbir Majeed Chaudhry (Circuits Syst. Signal Process., 2021)