Asymmetric Drain Underlap Schottky Barrier SOI MOSFET for Low-Power High Performance Nanoscale CMOS Circuits. - Ganesh C. Patil; Shafi Qureshi (ISVLSI, 2011)

Performance evaluation of mesh-based NoCs: Implementation of a new architecture and routing algorithm. - Sudhanshu Choudhary; Shafi Qureshi (Int. J. Autom. Comput., 2012)

Engineering buried oxide in dopant-segregated Schottky barrier SOI MOSFET for nanoscale CMOS circuits. - Ganesh C. Patil; Shafi Qureshi (Microelectron. Reliab., 2013)

Design and Analysis of Current Starved VCO Targeting SCL 180 nm CMOS Process. - Chandra Shekhar 006; Shafi Qureshi (iSES, 2018)

Design of Low-Power Reconfigurable Low-Noise Amplifier with Enhanced Linearity. - Rajani Bisht; Shafi Qureshi (TENCON, 2019)

Design of 50 MHz PLL using indigenous SCL 180 nm CMOS Technology. - Chandra Shekhar 006; Shafi Qureshi (iSES, 2021)