Memristor-based IMPLY logic design procedure. - Shahar Kvatinsky; Avinoam Kolodny; Uri C. Weiser; Eby G. Friedman (ICCD, 2011)

Sneak-path constraints in memristor crossbar arrays. - Yuval Cassuto; Shahar Kvatinsky; Eitan Yaakobi (ISIT, 2013)

TEAM: ThrEshold Adaptive Memristor Model. - Shahar Kvatinsky; Eby G. Friedman; Avinoam Kolodny; Uri C. Weiser (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Memristor-Based Multithreading. - Shahar Kvatinsky; Yuval H. Nacson; Yoav Etsion; Eby G. Friedman; Avinoam Kolodny; Uri C. Weiser (IEEE Comput. Archit. Lett., 2014)

Logic operations in memory using a memristive Akers array. - Yifat Levy; Jehoshua Bruck; Yuval Cassuto; Eby G. Friedman; Avinoam Kolodny; Eitan Yaakobi; Shahar Kvatinsky (Microelectron. J., 2014)

MAGIC - Memristor-Aided Logic. - Shahar Kvatinsky; Dmitry Belousov; Slavik Liman; Guy Satat; Nimrod Wald; Eby G. Friedman; Avinoam Kolodny; Uri C. Weiser (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies. - Shahar Kvatinsky; Guy Satat; Nimrod Wald; Eby G. Friedman; Avinoam Kolodny; Uri C. Weiser (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Resistive Associative Processor. - Leonid Yavits; Shahar Kvatinsky; Amir Morad; Ran Ginosar (IEEE Comput. Archit. Lett., 2015)

VTEAM: A General Model for Voltage-Controlled Memristors. - Shahar Kvatinsky; Misbah Ramadan; Eby G. Friedman; Avinoam Kolodny (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Memristor-Based Multilayer Neural Networks With Online Gradient Descent Training. - Daniel Soudry; Dotan Di Castro; Asaf Gal; Avinoam Kolodny; Shahar Kvatinsky (IEEE Trans. Neural Networks Learn. Syst., 2015)

Multistate Register Based on Resistive RAM. - Ravi Patel 001; Shahar Kvatinsky; Eby G. Friedman; Avinoam Kolodny (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A fully analog memristor-based neural network with online gradient training. - Eyal Rosenthal; Sergey Greshnikov; Daniel Soudry; Shahar Kvatinsky (ISCAS, 2016)

Write sneak-path constraints avoiding disturbs in memristor crossbar arrays. - Yuval Cassuto; Shahar Kvatinsky; Eitan Yaakobi (ISIT, 2016)

Improving energy efficiency of DRAM by exploiting half page row access. - Heonjae Ha; Ardavan Pedram; Stephen Richardson; Shahar Kvatinsky; Mark Horowitz (MICRO, 2016)

Evaluating programmable architectures for imaging and vision applications. - Artem Vasilyev; Nikhil Bhagdikar; Ardavan Pedram; Stephen Richardson; Shahar Kvatinsky; Mark Horowitz (MICRO, 2016)

Memory Processing Unit for in-memory processing. - Rotem Ben Hur; Shahar Kvatinsky (NANOARCH, 2016)

Logic design with unipolar memristors. - Elad Amrani; Avishay Drori; Shahar Kvatinsky (VLSI-SoC, 2016)

Logic with Unipolar Memristors - Circuits and Design Methodology. - Nimrod Wald; Elad Amrani; Avishay Drori; Shahar Kvatinsky (VLSI-SoC (Selected Papers), 2016)

A Systematic Approach to Blocking Convolutional Neural Networks. - Xuan Yang; Jing Pu; Blaine Burton Rister; Nikhil Bhagdikar; Stephen Richardson; Shahar Kvatinsky; Jonathan Ragan-Kelley; Ardavan Pedram; Mark Horowitz (CoRR, 2016)

Resistive GP-SIMD Processing-In-Memory. - Amir Morad; Leonid Yavits; Shahar Kvatinsky; Ran Ginosar (ACM Trans. Archit. Code Optim., 2016)

Information-Theoretic Sneak-Path Mitigation in Memristor Crossbar Arrays. - Yuval Cassuto; Shahar Kvatinsky; Eitan Yaakobi (IEEE Trans. Inf. Theory, 2016)

Modeling biochemical reactions and gene networks with memristors. - Hanna Abo Hanna; Loai Danial; Shahar Kvatinsky; Ramez Daniel (BioCAS, 2017)

Memristor for computing: Myth or reality? - Said Hamdioui; Shahar Kvatinsky; Gert Cauwenberghs; Lei Xie 005; Nimrod Wald; Siddharth Joshi 001; Hesham Mostafa Elsayed; Henk Corporaal; Koen Bertels (DATE, 2017)

Towards a memristive hardware secure hash function (MemHash). - Leonid Azriel; Shahar Kvatinsky (HOST, 2017)

Simple magic: Synthesis and in-memory Mapping of logic execution for memristor-aided logic. - Rotem Ben Hur; Nimrod Wald; Nishil Talati; Shahar Kvatinsky (ICCAD, 2017)

Rate-compatible and high-throughput architecture designs for encoding LDPC codes. - Nishil Talati; Zhiying Wang 001; Shahar Kvatinsky (ISCAS, 2017)

An RF memristor model and memristive single-pole double-throw switches. - Nicolás Wainstein; Shahar Kvatinsky (ISCAS, 2017)

Memristive logic: A framework for evaluation and comparison. - John Reuben; Rotem Ben Hur; Nimrod Wald; Nishil Talati; Ameer Haj Ali; Pierre-Emmanuel Gaillardon; Shahar Kvatinsky (PATMOS, 2017)

Dark Memory and Accelerator-Rich System Optimization in the Dark Silicon Era. - Ardavan Pedram; Stephen Richardson; Mark Horowitz; Sameh Galal; Shahar Kvatinsky (IEEE Des. Test, 2017)

Practical challenges in delivering the promises of real processing-in-memory machines. - Nishil Talati; Ameer Haj Ali; Rotem Ben Hur; Nimrod Wald; Ronny Ronen; Pierre-Emmanuel Gaillardon; Shahar Kvatinsky (DATE, 2018)

Efficient Algorithms for In-Memory Fixed Point Multiplication Using MAGIC. - Ameer Haj Ali; Rotem Ben Hur; Nimrod Wald; Shahar Kvatinsky (ISCAS, 2018)

Real-Time Trainable Data Converters for General Purpose Applications. - Loai Danial; Shahar Kvatinsky (NANOARCH, 2018)

DIDACTIC: A Data-Intelligent Digital-to-Analog Converter with a Trainable Integrated Circuit using Memristors. - Loai Danial; Nicolás Wainstein; Shraga Kraus; Shahar Kvatinsky (IEEE J. Emerg. Sel. Topics Circuits Syst., 2018)

Analysis of the row grounding technique in a memristor-based crossbar array. - Alexander Dozortsev; Israel Goldshtein; Shahar Kvatinsky (Int. J. Circuit Theory Appl., 2018)

Not in Name Alone: A Memristive Memory Processing Unit for Real In-Memory Processing. - Ameer Haj Ali; Rotem Ben Hur; Nimrod Wald; Ronny Ronen; Shahar Kvatinsky (IEEE Micro, 2018)

IMAGING: In-Memory AlGorithms for Image processiNG. - Ameer Haj Ali; Rotem Ben Hur; Nimrod Wald; Ronny Ronen; Shahar Kvatinsky (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

TIME - Tunable Inductors Using MEmristors. - Nicolás Wainstein; Shahar Kvatinsky (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Breaking Through the Speed-Power-Accuracy Tradeoff in ADCs Using a Memristive Neuromorphic Architecture. - Loai Danial; Nicolás Wainstein; Shraga Kraus; Shahar Kvatinsky (IEEE Trans. Emerg. Top. Comput. Intell., 2018)

A Taxonomy and Evaluation Framework for Memristive Logic. - John Reuben; Nishil Talati; Nimrod Wald; Rotem Ben Hur; Ameer Haj Ali; Pierre-Emmanuel Gaillardon; Shahar Kvatinsky (Handbook of Memristor Networks, 2019)

Real Processing-in-Memory with Memristive Memory Processing Unit (mMPU). - Shahar Kvatinsky (ASAP, 2019)

Logarithmic Neural Network Data Converters using Memristors for Biomedical Applications. - Loai Danial; Kanishka Sharma; Shivansh Dwivedi; Shahar Kvatinsky (BioCAS, 2019)

STT-ANGIE: Asynchronous True Random Number GEnerator Using STT-MTJ. - Ben Perach; Shahar Kvatinsky (DATE, 2019)

Performing Memristor-Aided Logic (MAGIC) using STT-MRAM. - Jeffry Louis; Barak Hoffer; Shahar Kvatinsky (ICECS, 2019)

The Missing Applications Found: Robust Design Techniques and Novel Uses of Memristors. - Marco Ottavi; Vishal Gupta 002; Saurabh Khandelwal; Shahar Kvatinsky; Jimson Mathew; Eugenio Martinelli; Abusaleh M. Jabir (IOLTS, 2019)

Delta-Sigma Modulation Neurons for High-Precision Training of Memristive Synapses in Deep Neural Networks. - Loai Danial; Sidharth Thomas; Shahar Kvatinsky (ISCAS, 2019)

A Dual-Band CMOS Low-Noise Amplifier using Memristor-Based Tunable Inductors. - Nicolás Wainstein; Tamir Tsabari; Yarden Goldin; Eilam Yalon; Shahar Kvatinsky (ISVLSI, 2019)

Real Processing-In-Memory with Memristive Memory Processing Unit. - Shahar Kvatinsky (SPACE, 2019)

A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories. - João Vieira; Edouard Giacomin; Yasir Mahmood Qureshi; Marina Zapater; Xifan Tang; Shahar Kvatinsky; David Atienza; Pierre-Emmanuel Gaillardon (VLSI-SoC, 2019)

Accelerating Inference on Binary Neural Networks with Digital RRAM Processing. - João Vieira; Edouard Giacomin; Yasir Mahmood Qureshi; Marina Zapater; Xifan Tang; Shahar Kvatinsky; David Atienza; Pierre-Emmanuel Gaillardon (VLSI-SoC (Selected Papers), 2019)

The Bitlet Model: Defining a Litmus Test for the Bitwise Processing-in-Memory Paradigm. - Kunal Korgaonkar; Ronny Ronen; Anupam Chattopadhyay; Shahar Kvatinsky (CoRR, 2019)

MTJ-Based Hardware Synapse Design for Quantized Deep Neural Networks. - Tzofnat Greenberg-Toledo; Ben Perach; Daniel Soudry; Shahar Kvatinsky (CoRR, 2019)

CONCEPT: A Column-Oriented Memory Controller for Efficient Memory and PIM Operations in RRAM. - Nishil Talati; Heonjae Ha; Ben Perach; Ronny Ronen; Shahar Kvatinsky (IEEE Micro, 2019)

Adaptive programming in multi-level cell ReRAM. - Misbah Ramadan; Nicolás Wainstein; Ran Ginosar; Shahar Kvatinsky (Microelectron. J., 2019)

Understanding the influence of device, circuit and environmental variations on real processing in memristive memory using Memristor Aided Logic. - Nimrod Wald; Shahar Kvatinsky (Microelectron. J., 2019)

A Robust Digital RRAM-Based Convolutional Block for Low-Power Image Processing and Learning Applications. - Edouard Giacomin; Tzofnat Greenberg-Toledo; Shahar Kvatinsky; Pierre-Emmanuel Gaillardon (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Supporting the Momentum Training Algorithm Using a Memristor-Based Synapse. - Tzofnat Greenberg-Toledo; Roee Mazor; Ameer Haj Ali; Shahar Kvatinsky (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

An Asynchronous and Low-Power True Random Number Generator Using STT-MTJ. - Ben Perach; Shahar Kvatinsky (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Modeling a Floating-Gate Memristive Device for Computer Aided Design of Neuromorphic Computing. - Loai Danial; Vasu Gupta; Evgeny Pikhay; Yakov Roizin; Shahar Kvatinsky (DATE, 2020)

Sensing with Memristive Complementary Resistive Switch: Modelling and Simulations. - Vishal Gupta 002; Danilo Pellegrini; Saurabh Khandelwal; Abusaleh M. Jabir; Shahar Kvatinsky; Eugenio Martinelli; Corrado Di Natale; Marco Ottavi (DFT, 2020)

Breaking the Conversion Wall in Mixed-Signal Systems Using Neuromorphic Data Converters. - Loai Danial; Shahar Kvatinsky (ECCTD, 2020)

CONTRA: Area-Constrained Technology Mapping Framework For Memristive Memory Processing Unit. - Debjyoti Bhattacharjee; Anupam Chattopadhyay; Srijit Dutta; Ronny Ronen; Shahar Kvatinsky (ICCAD, 2020)

A Pipelined Memristive Neural Network Analog-to-Digital Converter. - Loai Danial; Kanishka Sharma; Shahar Kvatinsky (ISCAS, 2020)

abstractPIM: Bridging the Gap Between Processing-In-Memory Technology and Instruction Set Architecture. - Adi Eliahu; Rotem Ben Hur; Ronny Ronen; Shahar Kvatinsky (VLSI-SOC, 2020)

abstractPIM: A Technology Backward-Compatible Compilation Flow for Processing-In-Memory. - Adi Eliahu; Rotem Ben Hur; Ronny Ronen; Shahar Kvatinsky (VLSI-SoC (Selected Papers), 2020)

X-MAGIC: Enhancing PIM Using Input Overwriting Capabilities. - Natan Peled; Rotem Ben Hur; Ronny Ronen; Shahar Kvatinsky (VLSI-SOC, 2020)

Cytomorphic Electronics With Memristors for Modeling Fundamental Genetic Circuits. - Hanna Abo Hanna; Loai Danial; Shahar Kvatinsky; Ramez Daniel (IEEE Trans. Biomed. Circuits Syst., 2020)

SIMPLER MAGIC: Synthesis and Mapping of In-Memory Logic Executed in a Single Row to Improve Throughput. - Rotem Ben Hur; Ronny Ronen; Ameer Haj Ali; Debjyoti Bhattacharjee; Adi Eliahu; Natan Peled; Shahar Kvatinsky (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Efficient Error-Correcting-Code Mechanism for High-Throughput Memristive Processing-in-Memory. - Orian Leitersdorf; Ben Perach; Ronny Ronen; Shahar Kvatinsky (DAC, 2021)

FiltPIM: In-Memory Filter for DNA Sequencing. - Marcel Khalifa; Rotem Ben Hur; Ronny Ronen; Orian Leitersdorf; Leonid Yavits; Shahar Kvatinsky (ICECS, 2021)

Making Memristive Processing-in-Memory Reliable. - Orian Leitersdorf; Ronny Ronen; Shahar Kvatinsky (ICECS, 2021)

(V)TEAM for SPICE Simulation of Memristive Devices With Improved Numerical Performance. - Dalibor Biolek; Zdenek Kolka; Viera Biolková; Zdenek Biolek; Shahar Kvatinsky (IEEE Access, 2021)

multiPULPly: A Multiplication Engine for Accelerating Neural Networks on Ultra-low-power Architectures. - Adi Eliahu; Ronny Ronen; Pierre-Emmanuel Gaillardon; Shahar Kvatinsky (ACM J. Emerg. Technol. Comput. Syst., 2021)

Improving Efficiency and Lifetime of Logic-in-Memory by Combining IMPLY and MAGIC Families. - Minhui Zou; Junlong Zhou; Jin Sun 001; Chengliang Wang 002; Shahar Kvatinsky (J. Syst. Archit., 2021)

Radiofrequency Switches Based on Emerging Resistive Memory Technologies - A Survey. - Nicolás Wainstein; Gina C. Adam; Eilam Yalon; Shahar Kvatinsky (Proc. IEEE, 2021)

Undergraduate Students' Attitudes Toward an Engineering Course that Integrates Several Levels of Abstraction. - Aharon Gero; Mohammed Ali Hadish; Shahar Kvatinsky (ICL (2), 2022)

MatPIM: Accelerating Matrix Operations with Memristive Stateful Logic. - Orian Leitersdorf; Ronny Ronen; Shahar Kvatinsky (ISCAS, 2022)

Enhancing Security of Memristor Computing System Through Secure Weight Mapping. - Minhui Zou; Junlong Zhou; Xiaotong Cui; Wei Wang 209; Shahar Kvatinsky (ISVLSI, 2022)

HashPIM: High-Throughput SHA-3 via Memristive Digital Processing-in-Memory. - Batel Oved; Orian Leitersdorf; Ronny Ronen; Shahar Kvatinsky (MOCAST, 2022)

Efficient Training of the Memristive Deep Belief Net Immune to Non-Idealities of the Synaptic Devices. - Wei Wang 209; Barak Hoffer; Tzofnat Greenberg-Toledo; Yang Li 203; Minhui Zou; Eric Herbelin; Ronny Ronen; Xiaoxin Xu; Yulin Zhao; Jianguo Yang; Shahar Kvatinsky (Adv. Intell. Syst., 2022)

Physical based compact model of Y-Flash memristor for neuromorphic computation. - Wei Wang 209; Loai Danial; Eric Herbelin; Barak Hoffer; Batel Oved; Tzofnat Greenberg-Toledo; Evgeny Pikhay; Yakov Roizin; Shahar Kvatinsky (CoRR, 2022)

Memristive deep belief neural network by silicon synapses. - Wei Wang 209; Loai Danial; Yang Li 203; Eric Herbelin; Evgeny Pikhay; Yakov Roizin; Barak Hoffer; Zhongrui Wang; Shahar Kvatinsky (CoRR, 2022)

PIMDB: Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics. - Ben Perach; Ronny Ronen; Benny Kimelfeld; Shahar Kvatinsky (CoRR, 2022)

Making Real Memristive Processing-in-Memory Faster and Reliable. - Shahar Kvatinsky (CoRR, 2022)

PartitionPIM: Practical Memristive Partitions for Fast Processing-in-Memory. - Orian Leitersdorf; Ronny Ronen; Shahar Kvatinsky (CoRR, 2022)

Performing Stateful Logic Using Spin-Orbit Torque (SOT) MRAM. - Barak Hoffer; Shahar Kvatinsky (CoRR, 2022)

Review of security techniques for memristor computing systems. - Minhui Zou; Nan Du 004; Shahar Kvatinsky (CoRR, 2022)

Stateful Logic using Phase Change Memory. - Barak Hoffer; Nicolás Wainstein; Christopher M. Neumann; Eric Pop; Eilam Yalon; Shahar Kvatinsky (CoRR, 2022)

The Bitlet Model: A Parameterized Analytical Model to Compare PIM and CPU Systems. - Ronny Ronen; Adi Eliahu; Orian Leitersdorf; Natan Peled; Kunal Korgaonkar; Anupam Chattopadhyay; Ben Perach; Shahar Kvatinsky (ACM J. Emerg. Technol. Comput. Syst., 2022)

C-AND: Mixed Writing Scheme for Disturb Reduction in 1T Ferroelectric FET Memory. - Mor M. Dahan; Evelyn T. Breyer; Stefan Slesazeck; Thomas Mikolajick; Shahar Kvatinsky (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

MultPIM: Fast Stateful Multiplication for Processing-in-Memory. - Orian Leitersdorf; Ronny Ronen; Shahar Kvatinsky (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Superconductive Logic Using 2ϕ - Josephson Junctions With Half Flux Quantum Pulses. - Issa Salameh; Eby G. Friedman; Shahar Kvatinsky (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

On Consistency for Bulk-Bitwise Processing-in-Memory. - Ben Perach; Ronny Ronen; Shahar Kvatinsky (HPCA, 2023)

Accelerating Relational Database Analytical Processing with Bulk-Bitwise Processing-in-Memory. - Ben Perach; Ronny Ronen; Shahar Kvatinsky (NEWCAS, 2023)

Enabling Relational Database Analytical Processing in Bulk-Bitwise Processing-In-Memory. - Ben Perach; Ronny Ronen; Shahar Kvatinsky (SOCC, 2023)

FourierPIM: High-Throughput In-Memory Fast Fourier Transform and Polynomial Multiplication. - Orian Leitersdorf; Yahav Boneh; Gonen Gazit; Ronny Ronen; Shahar Kvatinsky (CoRR, 2023)

ConvPIM: Evaluating Digital Processing-in-Memory through Convolutional Neural Network Acceleration. - Orian Leitersdorf; Ronny Ronen; Shahar Kvatinsky (CoRR, 2023)

CUDA-PIM: End-to-End Integration of Digital Processing-in-Memory from High-Level C++ to Microarchitectural Design. - Orian Leitersdorf; Ronny Ronen; Shahar Kvatinsky (CoRR, 2023)

TDPP: Two-Dimensional Permutation-Based Protection of Memristive Deep Neural Networks. - Minhui Zou; Zhenhua Zhu; Tzofnat Greenberg-Toledo; Orian Leitersdorf; Jiang Li 012; Junlong Zhou; Yu Wang 002; Nan Du 004; Shahar Kvatinsky (CoRR, 2023)

AritPIM: High-Throughput In-Memory Arithmetic. - Orian Leitersdorf; Dean Leitersdorf; Jonathan Gal; Mor M. Dahan; Ronny Ronen; Shahar Kvatinsky (IEEE Trans. Emerg. Top. Comput., 2023)

ClaPIM: Scalable Sequence Classification Using Processing-in-Memory. - Marcel Khalifa; Barak Hoffer; Orian Leitersdorf; Robert Hanhan; Ben Perach; Leonid Yavits; Shahar Kvatinsky (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A Concealable RRAM Physical Unclonable Function Compatible with In-Memory Computing. - Jiang Li 012; Yijun Cui; Chenghua Wang; Weiqiang Liu 001; Shahar Kvatinsky (DATE, 2024)

Assessing the Performance of Stateful Logic in 1-Selector-1-RRAM Crossbar Arrays. - Arjun Tyagi; Shahar Kvatinsky (ISCAS, 2024)

PyPIM: Integrating Digital Processing-in-Memory from Microarchitectural Design to Python Tensors. - Orian Leitersdorf; Ronny Ronen; Shahar Kvatinsky (MICRO, 2024)

Bitwise Logic Using Phase Change Memory Devices Based on the Pinatubo Architecture. - Noa Aflalo; Eilam Yalon; Shahar Kvatinsky (VLSID, 2024)

Transimpedance Amplifier with Automatic Gain Control Based on Memristors for Optical Signal Acquisition. - Sariel Hodisan; Shahar Kvatinsky (CoRR, 2024)

Roadmap to Neuromorphic Computing with Emerging Technologies. - Adnan Mehonic; Daniele Ielmini; Kaushik Roy 001; Onur Mutlu; Shahar Kvatinsky; Teresa Serrano-Gotarredona; Bernabé Linares-Barranco; Sabina Spiga; Sergey Savelev; Alexander G. Balanov; Nitin Chawla; Giuseppe Desoli; et al. (CoRR, 2024)

VVTEAM: A Compact Behavioral Model for Volatile Memristors. - Tanay Patni; Rishona Daniels; Shahar Kvatinsky (CoRR, 2024)

Accelerating DNA Read Mapping with Digital Processing-in-Memory. - Rotem Ben Hur; Orian Leitersdorf; Ronny Ronen; Lidor Goldshmidt; Idan Magram; Lior Kaplun; Leonid Yavitz; Shahar Kvatinsky (CoRR, 2024)

IMPACT:InMemory ComPuting Architecture Based on Y-FlAsh Technology for Coalesced Tsetlin Machine Inference. - Omar Ghazal; Wei Wang; Shahar Kvatinsky; Farhad Merchant; Alex Yakovlev; Rishad A. Shafik (CoRR, 2024)

Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics. - Ben Perach; Ronny Ronen; Benny Kimelfeld; Shahar Kvatinsky (IEEE Trans. Emerg. Top. Comput., 2024)

Experimental Demonstration of Non-Stateful In-Memory Logic With 1T1R OxRAM Valence Change Mechanism Memristors. - Henriette Padberg; Amir Regev; Giuseppe Piccolboni; Alessandro Bricalli; Gabriel Molas; Jean-Francois Nodin; Shahar Kvatinsky (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

TDPP: 2-D Permutation-Based Protection of Memristive Deep Neural Networks. - Minhui Zou; Zhenhua Zhu; Tzofnat Greenberg-Toledo; Orian Leitersdorf; Jiang Li 012; Junlong Zhou; Yu Wang 002; Nan Du 004; Shahar Kvatinsky (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Dependable Neuromorphic Computing-in-Memory Architectures. - Farhad Merchant; Ankit Bende; Markus Fritscher; Shahar Kvatinsky; Simranjeet Singh; Vikas Rana; Regina Dittmann; Keerthi Dorai Swamy Reddy; Christian Wenger; Fouwad Jamil Mir; Mottaqiallah Taouil; Manil Dev Gomony; et al. (ETS, 2025)

Stateful Logic In-Memory Using Gain-Cell eDRAM. - Barak Hoffer; Shahar Kvatinsky (NewCAS, 2025)

Preprocessing Methods for Memristive Reservoir Computing for Image Recognition. - Rishona Daniels; Duna Wattad; Ronny Ronen; David Saad; Shahar Kvatinsky (CoRR, 2025)

A Highly Reliable Dual-Mode RRAM PUF With Key Concealment Scheme. - Jiang Li 012; Yijun Cui; Chongyan Gu; Chenghua Wang; Weiqiang Liu 001; Shahar Kvatinsky (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)