Single-Event-Upset (SEU) Awareness in FPGA Routing. - Shahin Golshan; Elaheh Bozorgzadeh (DAC, 2007)

SEU-aware resource binding for modular redundancy based designs on FPGAs. - Shahin Golshan; Eli Bozorgzadeh (DATE, 2009)

Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems. - Shahin Golshan; Eli Bozorgzadeh; Benjamin Carrión Schäfer; Kazutoshi Wakabayashi; Houman Homayoun; Alexander V. Veidenbaum (ISLPED, 2010)

Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks. - Houman Homayoun; Shahin Golshan; Eli Bozorgzadeh; Alexander V. Veidenbaum; Fadi J. Kurdahi (ISQED, 2010)

Reliability-aware placement in SRAM-based FPGA for voltage scaling realization in the presence of process variations. - Shahin Golshan; Amin Khajeh; Houman Homayoun; Eli Bozorgzadeh; Ahmed M. Eltawil; Fadi J. Kurdahi (CODES+ISSS, 2011)

Process variation aware system-level load assignment for total energy minimization using stochastic ordering. - Shahin Golshan; Love Singhal; Eli Bozorgzadeh (ISQED, 2011)

On leakage power optimization in clock tree networks for ASICs and general-purpose processors. - Houman Homayoun; Shahin Golshan; Eli Bozorgzadeh; Alexander V. Veidenbaum; Fadi J. Kurdahi (Sustain. Comput. Informatics Syst., 2011)

SEU-Aware High-Level Data Path Synthesis and Layout Generation on SRAM-Based FPGAs. - Shahin Golshan; Hessam Kooti; Elaheh Bozorgzadeh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

MZZ-HVS: Multiple Sleep Modes Zig-Zag Horizontal and Vertical Sleep Transistor Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral Circuits. - Houman Homayoun; Avesta Sasan; Alexander V. Veidenbaum; Hsin-Cheng Yao; Shahin Golshan; Payam Heydari (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Hot peripheral thermal management to mitigate cache temperature variation. - Houman Homayoun; Mehryar Rahmatian; Vasileios Kontorinis; Shahin Golshan; Dean M. Tullsen (ISQED, 2012)