Average-Case Optimized Technology Mapping of One-Hot Domino CircuitsAverage-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits. - Wei-Chun Chou; Peter A. Beerel; Ran Ginosar; Rakefet Kol; Chris J. Myers; Shai Rotem; Ken S. Stevens; Kenneth Y. Yun (ASYNC, 1998)

RAPPID: An Asynchronous Instruction Length Decoder. - Shai Rotem; Ken S. Stevens; Charles Dike; Marly Roncken; Boris Agapiev; Ran Ginosar; Rakefet Kol; Peter A. Beerel; Chris J. Myers; Kenneth Y. Yun (ASYNC, 1999)

Relative Timing. - Ken S. Stevens; Shai Rotem; Ran Ginosar (ASYNC, 1999)

CAD Directions for High Performance Asynchronous Circuits. - Ken S. Stevens; Shai Rotem; Steven M. Burns; Jordi Cortadella; Ran Ginosar; Michael Kishinevsky; Marly Roncken (DAC, 1999)

CA-BIST for Asynchronous Circuits: A Case Study on the RAPPID Asynchronous Instruction Length Decoder. - Marly Roncken; Ken S. Stevens; Rajesh Pendurkar; Shai Rotem; Parimal Pal Chaudhuri (ASYNC, 2000)

An asynchronous instruction length decoder. - Kenneth S. Stevens; Shai Rotem; Ran Ginosar; Peter A. Beerel; Chris J. Myers; Kenneth Y. Yun; Rakefet Kol; Charles Dike; Marly Roncken (IEEE J. Solid State Circuits, 2001)

Coordinated transformations for high-level synthesis of high performance microprocessor blocks. - Sumit Gupta; Nick Savoiu; Nikil D. Dutt; Rajesh K. Gupta 001; Alexandru Nicolau; Timothy Kam; Michael Kishinevsky; Shai Rotem (DAC, 2002)

Relative timing [asynchronous design]. - Ken S. Stevens; Ran Ginosar; Shai Rotem (IEEE Trans. Very Large Scale Integr. Syst., 2003)

TAO: two-level atomicity for dynamic binary optimizations. - Edson Borin; Youfeng Wu; Cheng Wang 013; Wei Liu 014; Maurício Breternitz Jr.; Shiliang Hu; Esfir Natanzon; Shai Rotem; Roni Rosner (CGO, 2010)