Two Phase Write Scheme to Improve Low Voltage Write-ability in Medium-Density SRAMs. - M. Sultan M. Siddiqui; Shailendra Sharad; Yogendra Sharma; Amit Khanuja (VLSID, 2015)

Allowing Switching off Periphery Voltage Island Instead of Doing it per Instance Through Periphery VDD Collapse in SRAMs. - Krashna Nand Mishra; Ruchin Jain; Shailendra Sharad; Ravindra Shrivastava (VLSID, 2019)

A 38Mb/mm2 380/540mV Dual-Rail SRAM in 3nm-FinFET Technology. - Harold Pilo; John Barth 001; Kapil Dev Dwivedi; Peter Lee; Vikram Kumar; Prasanna Nalawar; Yogeshbhai Patel; Shailendra Sharad; Shakti Singh (ISSCC, 2025)