Underlap engineered eight-transistor SRAM cell for stronger data stability enhanced write ability and suppressed leakage power consumption. - Shairfe Muhammad Salahuddin; Volkan Kursun (ICECS, 2013)

Low-leakage hybrid FinFET SRAM cell with asymmetrical gate overlap / underlap bitline access transistors for enhanced read data stability. - Shairfe Muhammad Salahuddin; Hailong Jiao; Volkan Kursun (ISCAS, 2013)

A novel 6T SRAM cell with asymmetrically gate underlap engineered FinFETs for enhanced read data stability and write ability. - Shairfe Muhammad Salahuddin; Hailong Jiao; Volkan Kursun (ISQED, 2013)

High-speed and low-leakage FinFET SRAM cell with enhanced read and write voltage margins. - Shairfe Muhammad Salahuddin; Volkan Kursun (ISIC, 2014)

Write Assist SRAM Cell with Asymmetrical Bitline Access Transistors for Enhanced Data Stability and Write Ability. - Shairfe Muhammad Salahuddin; Volkan Kursun (J. Circuits Syst. Comput., 2016)

Thermally stable, packaged aware LV HKMG platforms benchmark to enable low power I/O for next 3D NAND generations. - Alessio Spessot; Shairfe Muhammad Salahuddin; Ricardo Escobar; Romain Ritzenthaler; Yang Xiang; Rahul Budhwani; Eugenio Dentoni Litta; Elena Capogreco; Joao P. Bastos; Yangyin Chen; Naoto Horiguchi (IMW, 2022)

Emerging Interconnect Exploration for SRAM Application Using Nonconventional H-Tree and Center-Pin Access. - Zhenlin Pei; Mahta Mayahinia; Hsiao-Hsuan Liu; Mehdi B. Tahoori; Shairfe Muhammad Salahuddin; Francky Catthoor; Zsolt Tokei; Chenyun Pan (ISQED, 2023)

3D SRAM Macro Design in 3D Nanofabric Process Technology. - Dawit Burusie Abdi; Shairfe Muhammad Salahuddin; Jürgen Bömmels; Edouard Giacomin; Pieter Weckx; Julien Ryckaert; Geert Hellings; Francky Catthoor (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active Interconnect. - Hsiao-Hsuan Liu; Carlo Gilardi; Shairfe Muhammad Salahuddin; Zhenlin Pei; Pieter Schuddinck; Yang Xiang; Pieter Weckx; Geert Hellings; Marie Garcia Bardon; Julien Ryckaert; Chenyun Pan; Subhasish Mitra; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)