VIS: A System for Verification and Synthesis. - Robert K. Brayton; Gary D. Hachtel; Alberto L. Sangiovanni-Vincentelli; Fabio Somenzi; Adnan Aziz; Szu-Tsung Cheng; Stephen A. Edwards; Sunil P. Khatri; Yuji Kukimoto; Abelardo Pardo; Shaz Qadeer; Rajeev K. Ranjan 001; et al. (CAV, 1996)

VIS. - Robert K. Brayton; Gary D. Hachtel; Alberto L. Sangiovanni-Vincentelli; Fabio Somenzi; Adnan Aziz; Szu-Tsung Cheng; Stephen A. Edwards; Sunil P. Khatri; Yuji Kukimoto; Abelardo Pardo; Shaz Qadeer; Rajeev K. Ranjan 001; et al. (FMCAD, 1996)

Conclusively verifying clock-domain crossings in very large hardware designs. - Guillaume Plassan; Hans-Jörg Peter; Katell Morin-Allory; Fahim Rahim; Shaker Sarwary; Dominique Borrione (VLSI-SoC, 2016)

Improving the Efficiency of Formal Verification: The Case of Clock-Domain Crossings. - Guillaume Plassan; Hans-Jörg Peter; Katell Morin-Allory; Shaker Sarwary; Dominique Borrione (VLSI-SoC (Selected Papers), 2016)