Optimization of Collective Communication in Intra-cell MPI. - M. K. Velamati; Arun Kumar 004; Naresh Jayam; Ganapathy Senthilkumar; Pallav K. Baruah; Raghunath Sharma; Shakti Kapoor; Ashok Srinivasan (HiPC, 2007)

Challenges in post-silicon verification of IBM's Cell/B.E. and other game processors. - Shakti Kapoor (HLDVT, 2007)

A Buffered-Mode MPI Implementation for the Cell BETM Processor. - Arun Kumar 004; Ganapathy Senthilkumar; Murali Krishna; Naresh Jayam; Pallav K. Baruah; Raghunath Sharma; Ashok Srinivasan; Shakti Kapoor (International Conference on Computational Science (1), 2007)

A Synchronous Mode MPI Implementation on the Cell BETM Architecture. - Murali Krishna; Arun Kumar 004; Naresh Jayam; Ganapathy Senthilkumar; Pallav K. Baruah; Raghunath Sharma; Shakti Kapoor; Ashok Srinivasan (ISPA, 2007)

Feasibility study of MPI implementation on the heterogeneous multi-core cell BETM architecture. - Arun Kumar 004; Naresh Jayam; Ashok Srinivasan; Ganapathy Senthilkumar; Pallav K. Baruah; Shakti Kapoor; Murali Krishna; Raghunath Sharma (SPAA, 2007)

Bridging pre-silicon verification and post-silicon validation. - Amir Nahir; Avi Ziv; Rajesh Galivanche; Alan J. Hu; Miron Abramovici; Albert Camilleri; Bob Bentley; Harry Foster; Valeria Bertacco; Shakti Kapoor (DAC, 2010)

Post-Silicon Validation of the IBM POWER8 Processor. - Amir Nahir; Manoj Dusanapudi; Shakti Kapoor; Kevin Reick; Wolfgang Roesner; Klaus-Dieter Schubert; Keith Sharp; Greg Wetli (DAC, 2014)

Debugging post-silicon fails in the IBM POWER8 bring-up lab. - Manoj Dusanapudi; S. Fields; Michael S. Floyd; Guy L. Guthrie; Ronald N. Kalla; Shakti Kapoor; Larry S. Leitner; Charles F. Marino; Joseph McGill; Amir Nahir; Kevin Reick; H. Shen; et al. (IBM J. Res. Dev., 2015)

A matrix math facility for Power ISA(TM) processors. - José E. Moreira; Kit Barton; Steven Battle; Peter Bergner; Ramon Bertran; Puneeth Bhat; Pedro Caldeira; David Edelsohn; Gordon C. Fossum; Brad Frey; Nemanja Ivanovic; Chip Kerchner; et al. (CoRR, 2021)