Architecture and Design of a High Performance SRAM for SOC Design. - Shobha Singh; Shamsi Azmi; Nutan Aarawal; Penaka Phani; Ansuman Rout (ASP-DAC/VLSI Design, 2002)

A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS. - Anuj Grover; G. S. Visweswaran; Chittoor R. Parthasarathy; Mohammad Daud; David Turgis; Bastien Giraud; Jean-Philippe Noel; Ivan Miro Panades; Guillaume Moritz; Edith Beigné; Philippe Flatresse; Promod Kumar; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)