Circuit Implementation of a 300-MHz 64-bit Second-generation CMOS Alpha CPU - William J. Bowhill; Shane L. Bell; Bradley J. Benschneider; Andrew J. Black; Sharon M. Britton; Ruben W. Castelino; Dale R. Donchin; John H. Edmondson; Harry R. Fair III; Paul E. Gronowski; Anil K. Jain 003; Patricia L. Kroesen; et al. (Digit. Tech. J., 1995)

Circuit implementation of a 600 MHz superscalar RISC microprocessor. - Mark Matson; Dan Bailey; Shane L. Bell; Larry L. Biro; Steve Butler; John Clouser; Jim Farrell; Mike Gowan; Donald A. Priore; Kathryn Wilcox (ICCD, 1998)