Hardware Acceleration of Matrix Multiplication over Small Prime Finite Fields. - Shane T. Fleming; David B. Thomas (ARC, 2013)

FPGA based control for real time systems. - Shane T. Fleming; David B. Thomas (FPL, 2013)

Heterogeneous Heartbeats: A framework for dynamic management of Autonomous SoCs. - Shane T. Fleming; David B. Thomas (FPL, 2014)

Is high level synthesis ready for business? A computational finance case study. - Gordon Inggs; Shane T. Fleming; David B. Thomas; Wayne Luk (FPT, 2014)

Transparent linking of compiled software and synthesized hardware. - David B. Thomas; Shane T. Fleming; George A. Constantinides; Dan R. Ghica (DATE, 2015)

System-level Linking of Synthesised Hardware and Compiled Software Using a Higher-order Type System. - Shane T. Fleming; David B. Thomas; George A. Constantinides; Dan R. Ghica (FPGA, 2015)

PushPush: Seamless integration of hardware and software objects via function calls over AXI. - Shane T. Fleming; Ivan Beretta; David B. Thomas; George A. Constantinides; Dan R. Ghica (FPL, 2015)

StitchUp: automatic control flow protection for high level synthesis circuits. - Shane T. Fleming; David B. Thomas (DAC, 2016)

Using Runahead Execution to Hide Memory Latency in High Level Synthesis. - Shane T. Fleming; David B. Thomas (FCCM, 2017)

Hardware Synthesis of Weakly Consistent C Concurrency. - Nadesh Ramanathan; Shane T. Fleming; John Wickerson; George A. Constantinides (FPGA, 2017)

Injecting FPGA Configuration Faults in Parallel. - Shane T. Fleming; David B. Thomas (FPT, 2018)

Accelerating Top-k ListNet Training for Ranking Using FPGA. - Qiang Li; Shane T. Fleming; David B. Thomas; Peter Y. K. Cheung (FPT, 2018)

EASY: Efficient Arbiter SYnthesis from Multi-threaded Code. - Jianyi Cheng; Shane T. Fleming; Yu Ting Chen; Jason Helge Anderson; George A. Constantinides (FPGA, 2019)

Accelerating Position-Aware Top-k ListNet for Ranking Under Custom Precision Regimes. - Qiang Li; Erwei Wang; Shane T. Fleming; David B. Thomas; Peter Y. K. Cheung (FPL, 2019)

Termination detection for fine-grained message-passing architectures. - Matthew Naylor; Simon W. Moore; Andrey Mokhov; David B. Thomas; Jonathan R. Beaumont; Shane T. Fleming; A. Theodore Markettos; Thomas Bytheway; Andrew D. Brown (ASAP, 2020)

General hardware multicasting for fine-grained message-passing architectures. - Matthew Naylor; Simon W. Moore; David B. Thomas; Jonathan R. Beaumont; Shane T. Fleming; Mark Vousden; A. Theodore Markettos; Thomas Bytheway; Andrew D. Brown (PDP, 2021)

Efficient Memory Arbitration in High-Level Synthesis From Multi-Threaded Code. - Jianyi Cheng; Shane T. Fleming; Yu Ting Chen; Jason Helge Anderson; John Wickerson; George A. Constantinides (IEEE Trans. Computers, 2022)

POETS: An Event-driven Approach to Dissipative Particle Dynamics: Implementing a Massively Compute-intensive Problem on a Novel Hard/Software Architecture. - Andrew D. Brown; Jonathan R. Beaumont; David B. Thomas; Julian C. Shillcock; Matthew Naylor; Graeme M. Bragg; Mark Vousden; Simon W. Moore; Shane T. Fleming (ACM Trans. Parallel Comput., 2023)

Honeycomb: Ordered Key-Value Store Acceleration on an FPGA-Based SmartNIC. - Junyi Liu; Aleksandar Dragojevic; Shane T. Fleming; Antonios Katsarakis; Dario Korolija; Igor Zablotchi; Ho-Cheung Ng; Anuj Kalia; Miguel Castro 001 (IEEE Trans. Computers, 2024)