Pipelined Fault Simulation on Parallel Machines Using the Circuit Flow Graph. - Shang-E Tai; Debashis Bhattacharya (ICCD, 1993)

A Three-Stage Partial Scan Design Method Using the Sequential Circuit Flow Graph. - Shang-E Tai; Debashis Bhattacharya (VLSI Design, 1994)

A three-stage partial scan design method to ease ATPG. - Shang-E Tai; Debashis Bhattacharya (J. Electron. Test., 1995)