VR-based teleautonomous system for AGV path guidance. - Chao-Huang Wei; Shang-Ping Chen (ICARCV, 2002)

A shifted-averaging VCO with precise multiphase outputs and low jitter operation. - Hsiang-Hui Chang; Shang-Ping Chen; Shen-Iuan Liu (ESSCIRC, 2003)

A 3.125-Gb/s clock and data recovery circuit for the 10-Gbase-LX4 Ethernet. - Rong-Jyi Yang; Shang-Ping Chen; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2004)

Fully Integrated CMOS SoC for 56/18/16 CD/DVD-dual/RAM Applications with On-Chip 4-LVDS Channel WSG and 1.5Gb/s SATA PHY. - Jyh-Shin Pan; Tse-Hsiang Hsu; Hao-Cheng Chen; Jong-Woei Chen; Bing-Yu Hsieh; Hong-Ching Chen; Wei-Hsuan Tu; Chi-Ming Chang; Roger Lee; Ching-Ho Chu; Yuan-Chin Liu; Chuan-Cheng Hsiao; et al. (ISSCC, 2006)

RTL-based Clock Recovery Architecture with All-Digital Duty-Cycle Correction. - Ping-Ying Wang; Meng-Ta Yang; Shang-Ping Chen; Meng-Hsueh Lin; Jing-Bing Yang (ISSCC, 2007)

A multi-format Blu-ray player SoC in 90nm CMOS. - Chi-Cheng Ju; Tsu-Ming Liu; Chih-Chieh Yang; Shih-Hung Lin; Kuo-Pin Lan; Chien-Hua Wu; Ting-Hsun Wei; Chi-Chin Lien; Jiun-Yuan Wu; Chih-Hao Hsiao; Te-Wei Chen; Yeh-Lin Chu; et al. (ISSCC, 2009)

26.6 A 2.667Gb/s DDR3 memory interface with asymmetric ODT on wirebond package and single-side-mounted PCB. - Shang-Ping Chen; Chih-Chien Hung; Qui-Ting Chen; Sheng-Ming Chang; Ming-Shi Liou; Bo-Wei Hsieh; Hsiang-I Huang; Brian Liu; Yan-Bin Luo (ISSCC, 2014)