An efficient embedded processor for object detection using ASIP methodology. - Shanlin Xiao; Tsuyoshi Isshiki; Dongju Li; Hiroaki Kunieda (ASAP, 2016)

Design of an Application Specific Instruction Set Processor for Real-Time Object Detection Using AdaBoost Algorithm. - Shanlin Xiao; Tsuyoshi Isshiki; Dongju Li; Hiroaki Kunieda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

HOG-Based Object Detection Processor Design Using ASIP Methodology. - Shanlin Xiao; Tsuyoshi Isshiki; Dongju Li; Hiroaki Kunieda (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017)

A Reconfigurable Process Engine for Flexible Convolutional Neural Network Acceleration. - Xiaobai Chen; Shanlin Xiao; Zhiyi Yu (APSIPA, 2018)

SPA: Stochastic Probability Adjustment for System Balance of Unsupervised SNNs. - Xingyu Yang; Mingyuan Meng; Shanlin Xiao; Zhiyi Yu (ICPR, 2020)

An Asynchronous Convolution Process Engine forVGG-16 Neural Network. - Junshu Lin; Weikun Liu; Xusheng Li; Shanlin Xiao; Zhiyi Yu (ICTA, 2020)

A Low-Power Processing Element Based on Asynchronous Data-Driven Bit-Serial Multiplier for CNNs. - Weikun Liu; Junshu Lin; Xusheng Li; Shanlin Xiao; Zhiyi Yu (ICTA, 2020)

Spiking Inception Module for Multi-layer Unsupervised Spiking Neural Networks. - Mingyuan Meng; Xingyu Yang; Shanlin Xiao; Zhiyi Yu (IJCNN, 2020)

A Low-Cost and High-Throughput NoC-Aware Chip-to-Chip Interconnection. - Wenkang Liao; Yuhao Guo; Shanlin Xiao; Zhiyi Yu (ISCAS, 2020)

BioSNet: A Fast-Learning and High-Robustness Unsupervised Biomimetic Spiking Neural Network. - Mingyuan Meng; Xingyu Yang; Shanlin Xiao; Zhiyi Yu (CoRR, 2020)

Low-Cost Adaptive Exponential Integrate-and-Fire Neuron Using Stochastic Computing. - Shanlin Xiao; Wei Liu 118; Yuhao Guo; Zhiyi Yu (IEEE Trans. Biomed. Circuits Syst., 2020)

NeuronLink: An Efficient Chip-to-Chip Interconnect for Large-Scale Neural Network Accelerators. - Shanlin Xiao; Yuhao Guo; Wenkang Liao; Huipeng Deng; Yi Luo; Huanliang Zheng; Jian Wang 080; Cheng Li; Gezi Li; Zhiyi Yu (IEEE Trans. Very Large Scale Integr. Syst., 2020)

3D-VNPU: A Flexible Accelerator for 2D/3D CNNs on FPGA. - Huipeng Deng; Jian Wang 080; Huafeng Ye; Shanlin Xiao; Xiangyu Meng 003; Zhiyi Yu (FCCM, 2021)

FWUA : A Flexible Winograd-Based Uniform Accelerator for 1D/2D/3D CNNs. - Jian Wang 080; Huipeng Deng; Huafeng Ye; Shanlin Xiao; Zhiyi Yu (ICTA, 2021)

A high throughput spatially coupled low density generator matrix coding system. - Ziyuan Luo; Qingyi Xie; Shanlin Xiao; Zhiyi Yu (ICTA, 2021)

High-Throughput Zipper Encoder for 800G Optical Communication System. - Qingyi Xie; Ziyuan Luo; Shanlin Xiao; Kai Wang; Zhiyi Yu (ICTA, 2021)

Dimension fusion: Dimension-level dynamically composable accelerator for convolutional neural networks. - Huipeng Deng; Jian Wang 080; Huafeng Ye; Shanlin Xiao; Xiangyu Meng 003; Zhiyi Yu (IEICE Electron. Express, 2021)

High-parallelism Inception-like Spiking Neural Networks for Unsupervised Feature Learning. - Mingyuan Meng; Xingyu Yang; Lei Bi 001; Jinman Kim; Shanlin Xiao; Zhiyi Yu (Neurocomputing, 2021)

Hand gesture recognition algorithm combining hand-type adaptive algorithm and effective-area ratio for efficient edge computing. - Qiang Zhang 034; Shanlin Xiao; Zhiyi Yu; Huanliang Zheng; Peng Wang (J. Electronic Imaging, 2021)

A Data-Driven Asynchronous Neural Network Accelerator. - Shanlin Xiao; Weikun Liu; Junshu Lin; Zhiyi Yu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

A Low-Power Asynchronous RISC-V Processor With Propagated Timing Constraints Method. - Zhiyu Li; Yuhao Huang; Longfeng Tian; Ruimin Zhu; Shanlin Xiao; Zhiyi Yu (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Balancing the Cost and Performance Trade-Offs in SNN Processors. - Huanliang Zheng; Yuhao Guo; Xingyu Yang; Shanlin Xiao; Zhiyi Yu (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

DFT Architecture for Click-Based Bundled-Data Asynchronous Circuits. - Ruimin Zhu; Zeyang Xu; Yuhao Huang; Shanlin Xiao; Zhiyi Yu (ICTA, 2022)

A dual-rail/single-rail hybrid system using null convention logic circuits. - Wenzha Yang; Yong Ma; Jiajie Yan; Yang Chen; Shanlin Xiao; Zhiyi Yu (Microelectron. J., 2022)

An Asynchronous Bundled-Data Template With Current Sensing Completion Detection Technique. - Yuhao Huang; Shanlin Xiao; Zhiyu Li; Zhiyi Yu (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Towards Efficient On-Chip Learning for Spiking Neural Networks Accelerator with Surrogate Gradient. - Kexin Huang; Wei Liu; Yue Liu; Shanlin Xiao; Zhiyi Yu (ICTA, 2023)

Towards Energy-Efficient Asynchronous Circuit Design with Flip-Flop-to-Latch Replacement. - Zeyang Xu; Shanlin Xiao; Lingfeng Zhou; Bohan Wang; Zhiyi Yu (ICTA, 2023)

Enabling energy-Efficient object detection with surrogate gradient descent in spiking neural networks. - Jilong Luo; Shanlin Xiao; Yinsheng Chen; Zhiyi Yu (CoRR, 2023)

An Efficient Asynchronous Circuits Design Flow with Backward Delay Propagation Constraint. - Lingfeng Zhou; Shanlin Xiao; Huiyao Wang; Jinghai Wang; Zeyang Xu; Bohan Wang; Zhiyi Yu (DATE, 2024)

Sparsespikformer: A Co-Design Framework for Token and Weight Pruning in Spiking Transformer. - Yue Liu; Shanlin Xiao; Bo Li; Zhiyi Yu (ICASSP, 2024)

Energy-Efficient and Fault-Tolerant Sparse Coding for Spiking Neural Networks Accelerator. - Bo Li; Wei Liu; Yue Liu; Xiao Huang; Zhiyi Yu; Shanlin Xiao (ICTA, 2024)

An FPGA-based QDI Asynchronous Circuits Design Methodology. - Guangyao Lin; Jinghai Wang; Zeyang Xu; Zhiyi Yu; Shanlin Xiao (ICTA, 2024)

Better-Than-Worst-Case: A Frequency Adaptation Asynchronous RISC-V Core With Vector Extension. - Lingfeng Zhou; Shanlin Xiao; Huiyao Wang; Jinghai Wang; Zeyang Xu; Bohan Wang; Zhiyi Yu (IEEE Trans. Very Large Scale Integr. Syst., 2024)

LAC: A Novel Lightweight Asynchronous Controller With Optimized Phase Shift. - Huiyao Wang; Shanlin Xiao; Lingfeng Zhou; Jinghai Wang; Zeyang Xu; Bohan Wang; Zhiyi Yu (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

SC-PLR: An Approximate Spiking Neural Network Accelerator With On-Chip Predictive Learning Rule. - Wei Liu 118; Shanlin Xiao; Yue Liu; Zhiyi Yu (IEEE Trans. Biomed. Circuits Syst., 2024)

Toward Efficient Asynchronous Circuits Design Flow Using Backward Delay Propagation Constraint. - Lingfeng Zhou; Shanlin Xiao; Huiyao Wang; Jinghai Wang; Zeyang Xu; Bohan Wang; Zhiyi Yu (IEEE Trans. Very Large Scale Integr. Syst., 2024)

SCSC: Leveraging Sparsity and Fault-Tolerance for Energy-Efficient Spiking Neural Networks. - Bo Li; Yue Liu; Wei Liu 118; Jinghai Wang; Xiao Huang; Zhiyi Yu; Shanlin Xiao (ASP-DAC, 2025)

Unsupervised Motion-Robust Self-Distillation Framework for Remote Physiological Measurement. - Anbang Liu; Shanlin Xiao; Wenming Zheng (ICASSP, 2025)

A Time-Borrowing Method for High-Performance Bundled-Data Asynchronous Circuits. - Bohan Wang; Zeyang Xu; Lingfeng Zhou; Huiyao Wang; Jinghai Wang; Zhiyi Yu; Shanlin Xiao (ISQED, 2025)

An End-to-End Bundled-Data Asynchronous Circuits Design Flow: From RTL to GDS. - Jinghai Wang; Shanlin Xiao; Jilong Luo; Bo Li; Lingfeng Zhou; Zhiyi Yu (IEEE Trans. Very Large Scale Integr. Syst., 2025)