Compaction of a Routed Channel on the Connection Machine. - Shantanu Ganguly; Vijay Pitchumani (DAC, 1989)

Clock distribution design and verification for PowerPC microprocessors. - Shantanu Ganguly; Shervin Hojat (ICCAD, 1995)

An Investigation of Power Delay Trade-Offs on PowerPC Circuits. - Qi Wang; Sarma B. K. Vrudhula; Shantanu Ganguly (DAC, 1997)

Divide & Conquer: A Strategy for Synthesis of Low Power Finite State Machines. - Aurobindo Dasgupta; Shantanu Ganguly (ICCD, 1997)

Clock Distribution Methodology for PowerPCTM Microprocessors. - Shantanu Ganguly; Daksh Lehther; Satyamurthy Pullela (J. VLSI Signal Process., 1997)

Power reduction and power-delay trade-offs using logic transformations. - Qi Wang; Sarma B. K. Vrudhula; Gary K. H. Yeap; Shantanu Ganguly (ACM Trans. Design Autom. Electr. Syst., 1999)

Building Digital Libraries: a how-to-do-it manual (Number 153). - Shantanu Ganguly (World Digit. Libr., 2009)

Issue editorial. - Shantanu Ganguly (World Digit. Libr., 2010)

Digital Information: order or anarchy? - Shantanu Ganguly (World Digit. Libr., 2010)

Open Educational Resources and Creative Commons Progress in Developing Countries: a study of Indian higher educational institutes. - Ratan Kumar Jha; Shesh Mishra; Vinay Shankar Prasad Sinha; Shantanu Ganguly (World Digit. Libr., 2023)