A clock-gating based capture power droop reduction methodology for at-speed scan testing. - Bo Yang; Amit Sanghani; Shantanu Sarangi; Chunsheng Liu (DATE, 2011)

Advanced test methodology for complex SoCs. - Pavan Kumar Datla Jagannadha; Mahmut Yilmaz; Milind Sonawane; Sailendra Chadalavada; Shantanu Sarangi; Bonita Bhaskaran; Ayub Abdollahian (ITC, 2016)

Flexible scan interface architecture for complex SoCs. - Milind Sonawane; Sailendra Chadalavada; Shantanu Sarangi; Amit Sanghani; Mahmut Yilmaz; Pavan Kumar Datla Jagannadha; Jonathon E. Colburn (VTS, 2016)

Dynamic docking architecture for concurrent testing and peak power reduction. - Milind Sonawane; Pavan Kumar Datla Jagannadha; Sailendra Chadalavada; Shantanu Sarangi; Mahmut Yilmaz; Amit Sanghani; Karthikeyan Natarajan; Jonathon E. Colburn; Anubhav Sinha (VTS, 2016)

At-speed capture global noise reduction & low-power memory test architecture. - Bonita Bhaskaran; Sailendra Chadalavada; Shantanu Sarangi; Nithin Valentine; Venkat Abilash Reddy Nerallapally; Ayub Abdollahian (VTS, 2017)

An Efficient Supervised Learning Method to Predict Power Supply Noise During At-speed Test. - Seyed Nima Mozaffari; Bonita Bhaskaran; Kaushik Narayanun; Ayub Abdollahian; Vinod Pagalone; Shantanu Sarangi; Jonathon E. Colburn (ITC, 2019)

Special Session: In-System-Test (IST) Architecture for NVIDIA Drive-AGX Platforms. - Pavan Kumar Datla Jagannadha; Mahmut Yilmaz; Milind Sonawane; Sailendra Chadalavada; Shantanu Sarangi; Bonita Bhaskaran; Shashank Bajpai; Venkat Abilash Reddy Nerallapally; Jayesh Pandey; Sam Jiang (VTS, 2019)

Hybrid Performance Modeling for Optimization of In-System-Structural-Test (ISST) Latency. - Milind Sonawane; Venkat Abilash Reddy Nerallapally; Alex Hsu; Shantanu Sarangi (VTS, 2019)

A Novel Graph-Coloring-Based Solution for Low-Power Scan Shift. - Saurabh Gupta 005; Bonita Bhaskaran; Shantanu Sarangi; Ayub Abdollahian; Jennifer Dworak (IEEE Des. Test, 2020)

On-Die Noise Measurement During Automatic Test Equipment (ATE) Testing and In-System-Test (IST). - Seyed Nima Mozaffari; Bonita Bhaskaran; Shantanu Sarangi; Suhas M. Satheesh; Kuo Lin Fu; Nithin Valentine; P. Manikandan; Mahmut Yilmaz (VTS, 2022)

NVIDIA MATHS: Mechanism to Access Test-Data over High-Speed Links. - Mahmut Yilmaz; Pavan Kumar Datla Jagannadha; Kaushik Narayanun; Shantanu Sarangi; Francisco Da Silva; Joe Sarmiento; Smbat Tonoyan; Ashwin Chintaluri; Animesh Khare; Milind Sonawane; Ashish Kumar; Anitha Kalva; et al. (VTS, 2022)

NVIDIA MATHS: Mechanism to Access Test-Data Over High-Speed Links. - Mahmut Yilmaz; Pavan Kumar Datla Jagannadha; Kaushik Narayanun; Shantanu Sarangi; Francisco Da Silva; Joe Sarmiento (IEEE Des. Test, 2023)

A Scalable & Cost Efficient Next-Gen Scan Architecture: Streaming Scan Test via NVIDIA MATHS. - Kunal Jain Mangilal; Mahmut Yilmaz; Vishal Agarwal; Shantanu Sarangi; Kaushik Narayanun (ITC, 2024)