Disjoint-Support Decomposition and Extraction for Interconnect-Driven Threshold Logic Synthesis. - Hao Chen; Shao-Chun Hung; Jie-Hong R. Jiang (DAC, 2019)

Power Supply Noise-Aware Scan Test Pattern Reshaping for At-Speed Delay Fault Testing of Monolithic 3D ICs *. - Shao-Chun Hung; Yi-Chen Lu; Sung Kyu Lim; Krishnendu Chakrabarty (ATS, 2020)

Design of a Reliable Power Delivery Network for Monolithic 3D ICs*. - Shao-Chun Hung; Krishnendu Chakrabarty (DATE, 2020)

Advances in Testing and Design-for-Test Solutions for M3D Integrated Circuits. - Sanmitra Banerjee; Arjun Chaudhuri; Shao-Chun Hung; Krishnendu Chakrabarty (DATE, 2021)

A DAG-Based Algorithm for Obstacle-Aware Topology-Matching On-Track Bus Routing. - Chen-Hao Hsu; Shao-Chun Hung; Hao Chen; Fan-Keng Sun; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Power Supply Noise-Aware At-Speed Delay Fault Testing of Monolithic 3-D ICs. - Shao-Chun Hung; Yi-Chen Lu; Sung Kyu Lim; Krishnendu Chakrabarty (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Graph Neural Network-based Delay-Fault Localization for Monolithic 3D ICs. - Shao-Chun Hung; Sanmitra Banerjee; Arjun Chaudhuri; Krishnendu Chakrabarty (DATE, 2022)

Observation Point Insertion Using Deep Learning. - Bonita Bhaskaran; Sanmitra Banerjee; Kaushik Narayanun; Shao-Chun Hung; Seyed Nima Mozaffari Mojaveri; Mengyun Liu; Gang Chen; Tung-Che Liang (ICCAD, 2022)

Fault Diagnosis for Resistive Random-Access Memory and Monolithic Inter-tier Vias in Monolithic 3D Integration. - Shao-Chun Hung; Arjun Chaudhuri; Sanmitra Banerjee; Krishnendu Chakrabarty (ITC, 2022)

Test-Point Insertion for Power-Safe Testing of Monolithic 3D ICs using Reinforcement Learning*. - Shao-Chun Hung; Arjun Chaudhuri; Krishnendu Chakrabarty (ETS, 2023)

Scan Cell Segmentation Based on Reinforcement Learning for Power-Safe Testing of Monolithic 3D ICs. - Shao-Chun Hung; Arjun Chaudhuri; Sanmitra Banerjee; Krishnendu Chakrabarty (ITC, 2023)

Special Session: Using Graph Neural Networks for Tier-Level Fault Localization in Monolithic 3D ICs *. - Shao-Chun Hung; Arjun Chaudhuri; Sanmitra Banerjee; Krishnendu Chakrabarty (VTS, 2023)

Transferable Graph Neural Network-Based Delay-Fault Localization for Monolithic 3-D ICs. - Shao-Chun Hung; Sanmitra Banerjee; Arjun Chaudhuri; Jinwoo Kim; Sung Kyu Lim; Krishnendu Chakrabarty (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Testing and Fault Diagnosis for Multi-level Resistive Random-Access Memory in Monolithic 3D Integration. - Shao-Chun Hung; Partho Bhoumik; Krishnendu Chakrabarty (VTS, 2024)

Fault Diagnosis for Resistive Random Access Memory and Monolithic Inter-Tier Vias in Monolithic 3-D Integration. - Shao-Chun Hung; Arjun Chaudhuri; Sanmitra Banerjee; Krishnendu Chakrabarty (IEEE Trans. Very Large Scale Integr. Syst., 2024)