Design and implementation of high performance dynamic 64-bit parallel adder with enhanced testability. - Wei Hwang; George Diedrich Gristede; Pia N. Sanda; Shao Y. Wang; David F. Heidel (CICC, 1998)

Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability. - Wei Hwang; George Diedrich Gristede; Pia N. Sanda; Shao Y. Wang; David F. Heidel (IEEE J. Solid State Circuits, 1999)