Redundant-wires-aware ECO timing and mask cost optimization. - Shao-Yun Fang; Tzuo-Fan Chien; Yao-Wen Chang (ICCAD, 2010)

Simultaneous flare level and flare variation minimization with dummification in EUVL. - Shao-Yun Fang; Yao-Wen Chang (DAC, 2012)

Native-Conflict and Stitch-Aware Wire Perturbation for Double Patterning Technology. - Shao-Yun Fang; Szu-Yu Chen; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Simultaneous OPC- and CMP-aware routing based on accurate closed-form modeling. - Shao-Yun Fang; Chung-Wei Lin; Guang-Wan Liao; Yao-Wen Chang (ISPD, 2013)

Graph-Based Subfield Scheduling for Electron-Beam Photomask Fabrication. - Shao-Yun Fang; Wei-Yu Chen; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

A Novel Layout Decomposition Algorithm for Triple Patterning Lithography. - Shao-Yun Fang; Yao-Wen Chang; Wei-Yu Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Cut mask optimization with wire planning in self-aligned multiple patterning full-chip routing. - Shao-Yun Fang (ASP-DAC, 2015)

Layout decomposition for Spacer-is-Metal (SIM) self-aligned double patterning. - Shao-Yun Fang; Yi-Shu Tai; Yao-Wen Chang (ASP-DAC, 2015)

EUV and e-beam manufacturability: challenges and solutions. - Yao-Wen Chang; Ru-Gun Liu; Shao-Yun Fang (DAC, 2015)

Provably Good Max-Min-m-neighbor-TSP-Based Subfield Scheduling for Electron-Beam Photomask Fabrication. - Zhi-Wen Lin; Shao-Yun Fang; Yao-Wen Chang; Wei-Cheng Rao; Chieh-Hsiung Kuan (ICCAD, 2015)

Stitch-Aware Routing for Multiple E-Beam Lithography. - Iou-Jen Liu; Shao-Yun Fang; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Design optimization considering guiding template feasibility and redundant via insertion for directed self-assembly. - Shao-Yun Fang; Yun-Xiang Hong (APCCAS, 2016)

Overlay-Aware Detailed Routing for Self-Aligned Double Patterning Lithography Using the Cut Process. - Iou-Jen Liu; Shao-Yun Fang; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Guiding template-aware routing considering redundant via insertion for directed self-assembly. - Kun-Lin Lin; Shao-Yun Fang (ASP-DAC, 2017)

Minimizing Cluster Number with Clip Shifting in Hotspot Pattern Classification. - Kuan-Jung Chen; Yu-Kai Chuang; Bo-Yi Yu; Shao-Yun Fang (DAC, 2017)

Simultaneous template assignment and layout decomposition using multiple bcp materials in DSA-MP lithography. - Kuo-Hao Wu; Shao-Yun Fang (ICCAD, 2017)

Simultaneous Guiding Template Optimization and Redundant via Insertion for Directed Self-Assembly. - Shao-Yun Fang; Yun-Xiang Hong; Yi-Zhen Lu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Design Optimization Considering Guiding Template Feasibility and Redundant Via Insertion for Directed Self-Assembly. - Kun-Lin Lin; Shao-Yun Fang; Yun-Xiang Hong (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Cut Mask Optimization With Wire Planning in Self-Aligned Multiple Patterning Full-Chip Routing. - Shao-Yun Fang; Kuo-Hao Wu (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Flip-chip routing with IO planning considering practical pad assignment constraints. - Tao-Chun Yu; Shao-Yun Fang (ASP-DAC, 2018)

PlanarONoC: concurrent placement and routing considering crossing minimization for optical networks-on-chip. - Yu-Kai Chuang; Kuan-Jung Chen; Kun-Lin Lin; Shao-Yun Fang; Bing Li 005; Ulf Schlichtmann (DAC, 2018)

RouteNet: routability prediction for mixed-size designs using convolutional neural network. - Zhiyao Xie; Yu-Hung Huang; Guan-Qi Fang; Haoxing Ren; Shao-Yun Fang; Yiran Chen 001; Nvidia Corporation (ICCAD, 2018)

Guiding Template-Induced Design Challenges in DSA-MP Lithography. - Shao-Yun Fang; Kuo-Hao Wu (ISVLSI, 2018)

Triple patterning lithography-aware detailed routing ensuring via layer decomposability. - Hua-Yi Wu; Shao-Yun Fang (VLSI-DAT, 2018)

Device Array Layout Synthesis With Nonlinear Gradient Compensation for a High-Accuracy Current-Steering DAC. - Tao-Chun Yu; Shao-Yun Fang; Chia-Ching Chen; Yulong Sun; Poki Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Provably Good Max-Min-m-Neighbor-TSP-Based Subfield Scheduling for Electron-Beam Photomask Fabrication. - Zhi-Wen Lin; Shao-Yun Fang; Yao-Wen Chang; Wei-Cheng Rao; Chieh-Hsiung Kuan (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Deep learning-based framework for comprehensive mask optimization. - Bo-Yi Yu; Yong Zhong; Shao-Yun Fang; Hung-Fei Kuo (ASP-DAC, 2019)

Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model. - Yu-Hung Huang; Zhiyao Xie; Guan-Qi Fang; Tao-Chun Yu; Haoxing Ren; Shao-Yun Fang; Yiran Chen 001; Jiang Hu (DATE, 2019)

Capacitance Minimization Clock Synthesis with Blockage-Avoiding Hybrid-Structure Network. - Chun-Wei Ho; Shao-Yun Fang (ISPACS, 2019)

Printability Enhancement with Color Balancing for Multiple Patterning Lithography. - Kuan-Jung Chen; Shao-Yun Fang (IEEE Trans. Emerg. Top. Comput., 2019)

Flip-Chip Routing With I/O Planning Considering Practical Pad Assignment Constraints. - Tao-Chun Yu; An-Jie Shih; Shao-Yun Fang (IEEE Trans. Very Large Scale Integr. Syst., 2019)

FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning. - Zhiyao Xie; Guan-Qi Fang; Yu-Hung Huang; Haoxing Ren; Yanqing Zhang 002; Brucek Khailany; Shao-Yun Fang; Jiang Hu; Yiran Chen 001; Erick Carvajal Barboza (ASP-DAC, 2020)

COALA: Concurrently Assigning Wire Segments to Layers for 2D Global Routing. - Yun-Jhe Jiang; Shao-Yun Fang (ICCAD, 2020)

Guiding Template Design for Lamellar DSA with Multiple Patterning and Self-Aligned Via Process. - An-Jie Shih; Shao-Yun Fang; Yi-Yu Liu (ICCAD, 2020)

Meshed Stack Via Design Considering Complicated Design Rules with Automatic Constraint Generation. - Kai-Chuan Yang; Tao-Chun Yu; Shao-Yun Fang; Teng-Yuan Cheng; Yang-Chun Liu; Cindy Chin-Fang Shen (ICCAD, 2020)

Lookahead Placement Optimization with Cell Library-based Pin Accessibility Prediction via Active Learning. - Tao-Chun Yu; Shao-Yun Fang; Hsien-Shih Chiu; Kai-Shun Hu; Philip Hui-Yuh Tai; Cindy Chin-Fang Shen; Henry Sheng (ISPD, 2020)

Via Pillar-aware Detailed Placement. - Yong Zhong; Tao-Chun Yu; Kai-Chuan Yang; Shao-Yun Fang (ISPD, 2020)

Stitch-Aware Routing Considering Smart Boundary for Multiple E-Beam Lithography. - Chih-Hsiang Hsu; Shao-Yun Fang (VLSI-DAT, 2020)

From IC Layout to Die Photo: A CNN-Based Data-Driven Approach. - Hao-Chiang Shao; Chao-Yi Peng; Jun-Rei Wu; Chia-Wen Lin; Shao-Yun Fang; Pin-Yen Tsai; Yan-Hsiu Liu (CoRR, 2020)

Obstacle-Avoiding Open-Net Connector With Precise Shortest Distance Estimation. - Guan-Qi Fang; Yong Zhong; Yi-Hao Cheng; Shao-Yun Fang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Obstacle-Avoiding Length-Matching Bus Routing Considering Nonuniform Track Resources. - Yi-Hao Cheng; Tao-Chun Yu; Shao-Yun Fang (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Machine Learning-based Structural Pre-route Insertability Prediction and Improvement with Guided Backpropagation. - Tao-Chun Yu; Shao-Yun Fang; Hsien-Shih Chiu; Kai-Shun Hu; Chin-Hsiung Hsu; Philip Hui-Yuh Tai; Cindy Chin-Fang Shen (ASP-DAC, 2021)

RobustONoC: Fault-Tolerant Optical Networks-on-Chip with Path Backup and Signal Reflection. - Yu-Kai Chuang; Yong Zhong; Yi-Hao Cheng; Bo-Yi Yu; Shao-Yun Fang; Bing Li 005; Ulf Schlichtmann (ISQED, 2021)

Placement-guided pin layout substitution for routability optimization. - Jia-Hong Chang; Shao-Yun Fang (Microelectron. J., 2021)

Manufacturability Enhancement With Dummy via Insertion for DSA-MP Lithography Using Multiple BCP Materials. - Yun-Jhe Jiang; Kuo-Hao Wu; Shao-Yun Fang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

From IC Layout to Die Photograph: A CNN-Based Data-Driven Approach. - Hao-Chiang Shao; Chao-Yi Peng; Jun-Rei Wu; Chia-Wen Lin; Shao-Yun Fang; Pin-Yen Tsai; Yan-Hsiu Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Pin Accessibility Prediction and Optimization With Deep-Learning-Based Pin Pattern Recognition. - Tao-Chun Yu; Shao-Yun Fang; Hsien-Shih Chiu; Kai-Shun Hu; Philip Hui-Yuh Tai; Cindy Chin-Fang Shen; Henry Sheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

A Robust Quantum Layout Synthesis Algorithm with a Qubit Mapping Checker. - Tsou-An Wu; Yun-Jhe Jiang; Shao-Yun Fang (ICCAD, 2022)

SpeedER: A Supervised Encoder-Decoder Driven Engine for Effective Resistance Estimation of Power Delivery Networks. - Bing-Yue Wu; Shao-Yun Fang; Hsiang-Wen Chang; Peter Wei (MLCAD, 2022)

Demand-Driven Multi-Target Sample Preparation on Resource-Constrained Digital Microfluidic Biochips. - Sudip Poddar; Sukanta Bhattacharjee; Shao-Yun Fang; Tsung-Yi Ho; Bhargab B. Bhattacharya (ACM Trans. Design Autom. Electr. Syst., 2022)

MIA-Aware Detailed Placement and VT Reassignment for Leakage Power Optimization. - Hung-Chun Lin; Shao-Yun Fang (ASP-DAC, 2023)

Data-Driven Approaches for Process Simulation and Optical Proximity Correction. - Hao-Chiang Shao; Chia-Wen Lin; Shao-Yun Fang (ASP-DAC, 2023)

Lamellar DSA-aware Detailed Routing Considering Double Patterning and Short Template Minimization. - Kuei-Lin Wu; Shao-Yun Fang (DAC, 2023)

Mitigating Layout Dependent Effect-induced Timing Risk in Multi-Row-Height Detailed Placement. - Li-Chen Wang; Shao-Yun Fang (DATE, 2023)

Spacing Cost-aware Optimal and Efficient Mixed-Cell-Height Detailed Placement for DFM Considerations. - Da-Wei Huang; Ying-Jie Jiang; Shao-Yun Fang (ICCAD, 2023)

Advanced Design Methodologies for Directed Self-Assembly. - Shao-Yun Fang (ISPD, 2023)

Pin Access-Oriented Concurrent Detailed Routing. - Yun-Jhe Jiang; Shao-Yun Fang (ISPD, 2023)

COALA: Concurrently Assigning Wire Segments to Layers for 2-D Global Routing. - Yun-Jhe Jiang; Shao-Yun Fang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Keeping Deep Lithography Simulators Updated: Global-Local Shape-Based Novelty Detection and Active Learning. - Hao-Chiang Shao; Hsing-Lei Ping; Kuo-Shiuan Chen; Weng-Tai Su; Chia-Wen Lin; Shao-Yun Fang; Pin-Yian Tsai; Yan-Hsiu Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Enhanced and Efficient Guiding Template Design for Lamellar DSA With Graph Monomorphism. - Yi-Sian Ciou; An-Jie Shih; Shao-Yun Fang; Yi-Yu Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Concurrent Detailed Routing with Pin Pattern Re-generation for Ultimate Pin Access Optimization. - Ying-Jie Jiang; Shao-Yun Fang (DAC, 2024)

Overview of 2024 CAD contest at ICCAD. - Shao-Yun Fang; Yi-Yu Liu; Chung-Kuan Cheng; Tsun-Ming Tseng (ICCAD, 2024)

SMT-based Layout Synthesis for Silicon-based Quantum Computing with Crossbar Architecture. - Sheng-Tan Huang; Ying-Jie Jiang; Shao-Yun Fang; Chung-Kuan Cheng (ICCAD, 2024)

Practical Mixed-Cell-Height Legalization Considering Vertical Cell Abutment Constraint. - Teng-Ping Huang; Shao-Yun Fang (ISPD, 2024)

CPONoC: Critical Path-aware Physical Implementation for Optical Networks-on-Chip. - Yan-Ting Chen; Zhidan Zheng; Shao-Yun Fang; Tsun-Ming Tseng; Ulf Schlichtmann (ASP-DAC, 2025)

Paired-Spacing-Constrained Package Routing with Net Ordering Optimization. - Yi-Sian Ciou; Ying-Jie Jiang; Yi-Yu Liu; Shao-Yun Fang; Wen-Hao Liu 001 (ASP-DAC, 2025)

Pin Access-aware Multiple Via Pillar Co-Design for Routability Optimization. - Man-Ling Hong; Ying-Jie Jiang; Shao-Yun Fang (ASP-DAC, 2025)

Via Fabrication with Multi-Row Guiding Templates Using Lamellar DSA. - Yun-Na Tsai; Shao-Yun Fang (ASP-DAC, 2025)

LithoHoD: A Litho Simulator-Powered Framework for IC Layout Hotspot Detection. - Hao-Chiang Shao; Guan-Yu Chen; Yu-Hsien Lin; Chia-Wen Lin; Shao-Yun Fang; Pin-Yian Tsai; Yan-Hsiu Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Layout Synthesis for Quantum Circuits Considering Toffoli Gate Decomposition. - Po-Wei Chen; Sheng-Tan Huang; Shao-Yun Fang (ACM Trans. Design Autom. Electr. Syst., 2025)