DATuner: An Extensible Distributed Autotuning Framework for FPGA Design and Design Automation: (Abstract Only). - Gai Liu; Ecenur Ustun; Shaojie Xiang; Chang Xu 005; Guojie Luo; Zhiru Zhang (FPGA, 2018)

LAMDA: Learning-Assisted Multi-stage Autotuning for FPGA Design Closure. - Ecenur Ustun; Shaojie Xiang; Jinny Gui; Cunxi Yu; Zhiru Zhang (FCCM, 2019)

Study on Computational Experiments of C2C Tax Compliance based on Information of Cybermediaries. - Feng Xiong; Shaojie Xiang; Peng Jin (Adv. Complex Syst., 2019)

Dagger: Towards Efficient RPCs in Cloud Microservices With Near-Memory Reconfigurable NICs. - Nikita Lazarev; Neil Adit; Shaojie Xiang; Zhiru Zhang; Christina Delimitrou (IEEE Comput. Archit. Lett., 2020)

Dagger: efficient and fast RPCs in cloud microservices with near-memory reconfigurable NICs. - Nikita Lazarev; Shaojie Xiang; Neil Adit; Zhiru Zhang; Christina Delimitrou (ASPLOS, 2021)

Dagger: Accelerating RPCs in Cloud Microservices Through Tightly-Coupled Reconfigurable NICs. - Nikita Lazarev; Shaojie Xiang; Neil Adit; Zhiru Zhang; Christina Delimitrou (CoRR, 2021)

Programming and Synthesis for Software-defined FPGA Acceleration: Status and Future Prospects. - Yi-Hsiang Lai; Ecenur Ustun; Shaojie Xiang; Zhenman Fang; Hongbo Rong; Zhiru Zhang (ACM Trans. Reconfigurable Technol. Syst., 2021)

Accelerator design with decoupled hardware customizations: benefits and challenges: invited. - Debjit Pal; Yi-Hsiang Lai; Shaojie Xiang; Niansong Zhang; Hongzheng Chen; Jeremy Casas; Pasquale Cocchini; Zhenkun Yang; Jin Yang 006; Louis-Noël Pouchet; Zhiru Zhang (DAC, 2022)

HeteroFlow: An Accelerator Programming Model with Decoupled Data Placement for Software-Defined FPGAs. - Shaojie Xiang; Yi-Hsiang Lai; Yuan Zhou; Hongzheng Chen; Niansong Zhang; Debjit Pal; Zhiru Zhang (FPGA, 2022)

A Comprehensive Evaluation of FPGA-Based Spatial Acceleration of LLMs. - Hongzheng Chen; Jiahao Zhang; Yixiao Du; Shaojie Xiang; Zichao Yue; Niansong Zhang; Yaohui Cai; Zhiru Zhang (FPGA, 2024)

RapidStream IR: Infrastructure for FPGA High-Level Physical Synthesis. - Jason Lau; Yuanlong Xiao; Yutong Xie 011; Yuze Chi; Linghao Song; Shaojie Xiang; Michael Lo; Zhiru Zhang; Jason Cong; Licheng Guo (ICCAD, 2024)

Allo: A Programming Model for Composable Accelerator Design. - Hongzheng Chen; Niansong Zhang; Shaojie Xiang; Zhichen Zeng 002; Mengjia Dai; Zhiru Zhang (Proc. ACM Program. Lang., 2024)

ARIES: An Agile MLIR-Based Compilation Flow for Reconfigurable Devices with AI Engines. - Jinming Zhuang; Shaojie Xiang; Hongzheng Chen; Niansong Zhang; Zhuoping Yang; Tony Mao; Zhiru Zhang; Peipei Zhou 001 (FPGA, 2025)

Understanding the Potential of FPGA-based Spatial Acceleration for Large Language Model Inference. - Hongzheng Chen; Jiahao Zhang; Yixiao Du; Shaojie Xiang; Zichao Yue; Niansong Zhang; Yaohui Cai; Zhiru Zhang (ACM Trans. Reconfigurable Technol. Syst., 2025)