A noise optimization technique for codesign of CMOS radio-frequency low noise amplifiers and low-quality spiral inductors. - Shaolei Quan; Chin-Long Wey (ACM Great Lakes Symposium on VLSI, 2004)

A power-optimized 64-bit priority encoder utilizing parallel priority look-ahead. - Cheong Kun; Shaolei Quan; Andrew Mason (ISCAS (2), 2004)

Design of a CMOS Operational Amplifier for Extreme-Voltage Stress Test. - Shaolei Quan; Qiang Qiang; Chin-Long Wey (Asian Test Symposium, 2005)

Design of a CMOS Operational Amplifier Amenable to Extreme Voltage Stress. - Shaolei Quan; Meng-Yao Liu; Chin-Long Wey (DFT, 2005)

A novel reconfigurable architecture of low-power unsigned multiplier for digital signal processing. - Shaolei Quan; Qiang Qiang; Chin-Long Wey (ISCAS (4), 2005)

Reliability enhancement of CMOS SRAMs. - Chin-Long Wey; Meng-Yao Liu; Shaolei Quan (MTDT, 2005)

Design of Reliable CMOS Phase-Locked Loops. - Chin-Long Wey; Chi-Shu Huang; Shaolei Quan (ICECS, 2006)

A 1.0625-to-14.025Gb/s multimedia transceiver with full-rate source-series-terminated transmit driver and floating-tap decision-feedback equalizer in 40nm CMOS. - Shaolei Quan; Freeman Zhong; Wing Liu; Pervez M. Aziz; Tai Jing; Jen Dong; Chintan Desai; Hairong Gao; Monica Garcia; Gary Hom; Tony Huynh; Hiroshi Kimura; et al. (ISSCC, 2011)

A 1.0625 14.025 Gb/s Multi-Media Transceiver With Full-Rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40 nm CMOS. - Freeman Zhong; Shaolei Quan; Wing Liu; Pervez M. Aziz; Tai Jing; Jen Dong; Chintan Desai; Hairong Gao; Monica Garcia; Gary Hom; Tony Huynh; Hiroshi Kimura; et al. (IEEE J. Solid State Circuits, 2011)