MaPU: A novel mathematical computing architecture. - Donglin Wang; Xueliang Du; Leizu Yin; Chen Lin; Hong Ma; Weili Ren; Huijuan Wang; Xingang Wang; Shaolin Xie; Lei Wang; Zijun Liu; Tao Wang; et al. (HPCA, 2016)

A self-indexed register file for efficient arithmetical computing hardware. - Lei Yang; Shaolin Xie; Zijun Liu; Xueliang Du; Donglin Wang (CEEC, 2017)

FBNA: A Fully Binarized Neural Network Accelerator. - Peng Guo; Hong Ma; Ruizhi Chen; Pin Li; Shaolin Xie; Donglin Wang (FPL, 2018)

Low Latency Spiking ConvNets with Restricted Output Training and False Spike Inhibition. - Ruizhi Chen; Hong Ma; Peng Guo; Shaolin Xie; Pin Li; Donglin Wang (IJCNN, 2018)

Fast and Efficient Deep Sparse Multi-Strength Spiking Neural Networks with Dynamic Pruning. - Ruizhi Chen; Hong Ma; Shaolin Xie; Peng Guo; Pin Li; Donglin Wang (IJCNN, 2018)

Parallel Polar Encoding in 5G Communication. - Yang Guo; Shaolin Xie; Zijun Liu; Lei Yang; Donglin Wang (ISCC, 2018)

The BaseJump Manycore Accelerator Network. - Shaolin Xie; Michael B. Taylor (CoRR, 2018)

The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips. - Scott Davidson 004; Shaolin Xie; Christopher Torng; Khalid Al-Hawaj; Austin Rovinski; Tutu Ajayi; Luis Vega; Chun Zhao; Ritchie Zhao; Steve Dai; Aporva Amarnath; Bandhav Veluri; et al. (IEEE Micro, 2018)

Extreme Datacenter Specialization for Planet-Scale Computing: ASIC Clouds. - Shaolin Xie; Scott Davidson 004; Ikuo Magaki; Moein Khazraee; Luis Vega; Lu Zhang; Michael B. Taylor (ACM SIGOPS Oper. Syst. Rev., 2018)

A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm. - Subhankar Pal; Dong-Hyeon Park; Siying Feng; Paul Gao 001; Jielun Tan; Austin Rovinski; Shaolin Xie; Chun Zhao; Aporva Amarnath; Timothy Wesley; Jonathan Beaumont; Kuan-Yu Chen 001; et al. (VLSI Circuits, 2019)

A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS. - Austin Rovinski; Chun Zhao; Khalid Al-Hawaj; Paul Gao 001; Shaolin Xie; Christopher Torng; Scott Davidson 004; Aporva Amarnath; Luis Vega; Bandhav Veluri; Anuj Rao; Tutu Ajayi; et al. (VLSI Circuits, 2019)

A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator. - Dong-Hyeon Park; Subhankar Pal; Siying Feng; Paul Gao 001; Jielun Tan; Austin Rovinski; Shaolin Xie; Chun Zhao; Aporva Amarnath; Timothy Wesley; Jonathan Beaumont; Kuan-Yu Chen 001; et al. (IEEE J. Solid State Circuits, 2020)

Scalable, Programmable and Dense: The HammerBlade Open-Source RISC-V Manycore. - Dai Cheol Jung; Max Ruttenberg; Paul Gao 001; Scott Davidson 004; Daniel Petrisko; Kangli Li; Aditya K. Kamath; Lin Cheng; Shaolin Xie; Peitian Pan; Zhongyuan Zhao 004; Zichao Yue; et al. (ISCA, 2024)

QuIT your B+-tree for the Quick Insertion Tree. - Aneesh Raman; Konstantinos Karatsenidis; Shaolin Xie; Matthaios Olma; Subhadeep Sarkar; Manos Athanassoulis (EDBT, 2025)

LIMAO: A Framework for Lifelong Modular Learned Query Optimization. - Qihan Zhang; Shaolin Xie; Ibrahim Sabek (CoRR, 2025)