Fault Testing in Combinational Cellular Arrays - Sharad C. Seth (1970)

On a Relation Between Algebraic Programs and Turing Machines. - James M. Steckelberg; Sharad C. Seth (Inf. Process. Lett., 1977)

Diagnosis of Faults in Linear Tree Networks. - Sharad C. Seth; Kolar L. Kodandapani (IEEE Trans. Computers, 1977)

On Combinational Networks with Restricted Fan-Out. - Kolar L. Kodandapani; Sharad C. Seth (IEEE Trans. Computers, 1978)

LSI product quality and fault coverage. - Vishwani D. Agrawal; Sharad C. Seth; Prathima Agrawal (DAC, 1981)

A Graph Model for Pattern-Sensitive Faults in Random Access Memories. - Sharad C. Seth; K. Narayanaswamy (IEEE Trans. Computers, 1981)

A Simplified Method to Calculate Failure Times in Fault-Tolerant Systems. - Sharad C. Seth; Lester Lipsky (IEEE Trans. Computers, 1983)

An Analysis of the Use of Rademacher-Walsh Spectrum in Compact Testing. - Ten-Chuan Hsiao; Sharad C. Seth (IEEE Trans. Computers, 1984)

Characterizing the LSI Yield Equation from Wafer Test Data. - Sharad C. Seth; Vishwani D. Agrawal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984)

Predicting Fault Coverage from Probabilistic Testability. - Sharad C. Seth (ITC, 1985)

Decoding Substitution Ciphers by Means of Word Matching with Application to OCR. - George Nagy; Sharad C. Seth; Kent L. Einspahr (IEEE Trans. Pattern Anal. Mach. Intell., 1987)

A fast fault simulation algorithm for combinational circuits. - Wuudiann Ke; Sharad C. Seth; Bhargab B. Bhattacharya (ICCAD, 1988)

Testability Analysis of Synchronous Sequential Circuits Based on Structural Data. - Raghu V. Hudli; Sharad C. Seth (ITC, 1989)

A new model for computation of probabilistic testability in combinational circuits. - Sharad C. Seth; Vishwani D. Agrawal (Integr., 1989)

Design of Parity Testable Combinational Circuits. - Bhargab B. Bhattacharya; Sharad C. Seth (IEEE Trans. Computers, 1989)

Signal Probabilities in AND-OR Trees. - Lester Lipsky; Sharad C. Seth (IEEE Trans. Computers, 1989)

An experimental study on reject ratio prediction for VLSI circuits: Kokomo revisited. - Dharam Vir Das; Sharad C. Seth; Paul T. Wagner; John C. Anderson; Vishwani D. Agrawal (ITC, 1990)

High-level microprogramming: an optimizing C compiler for a processing element of a CAD accelerator. - Paul Kenyon; Prathima Agrawal; Sharad C. Seth (MICRO, 1990)

A Statistical Theory of Digital Circuit Testability. - Sharad C. Seth; Vishwani D. Agrawal; Hassan Farhat (IEEE Trans. Computers, 1990)

Estimating the Quality of Manufactured Digital Sequential Circuits. - Dharam Vir Das; Sharad C. Seth; Vishwani D. Agrawal (ITC, 1991)

DynaTAPP: dynamic timing analysis with partial path activation in sequential circuits. - Prathima Agrawal; Vishwani D. Agrawal; Sharad C. Seth (EURO-DAC, 1992)

A New Method for Generating Tests for Delay Faults in Non-Scan Circuits. - Prathima Agrawal; Vishwani D. Agrawal; Sharad C. Seth (VLSI Design, 1992)

A Switch-Level Test Generation System. - Kent L. Einspahr; Sharad C. Seth (VLSI Design, 1992)

A Prototype Document Image Analysis System for Technical Journals. - George Nagy; Sharad C. Seth; Mahesh Viswanathan 002 (Computer, 1992)

Clock partitioning for testability. - Kent L. Einspahr; Sharad C. Seth; Vishwani D. Agrawal (Great Lakes Symposium on VLSI, 1993)

Generating Tests for Delay Faults in Nonscan Circuits. - Prathima Agrawal; Vishwani D. Agrawal; Sharad C. Seth (IEEE Des. Test Comput., 1993)

Syntactic Segmentation and Labeling of Digitized Pages from Technical Journals. - Mukkai S. Krishnamoorthy; George Nagy; Sharad C. Seth; Mahesh Viswanathan 002 (IEEE Trans. Pattern Anal. Mach. Intell., 1993)

Accurate computation of field reject ratio based on fault latency. - D. Das; Sharad C. Seth; Vishwani D. Agrawal (IEEE Trans. Very Large Scale Integr. Syst., 1993)

Logic Simulation Using an Asynchronous Parallel Discrete-Event Simulation Model on a SIMD Machine. - Sharad C. Seth; Lee Gowen; Matt Payne; Don Sylwester (VLSI Design, 1994)

Isolating symbols from connection lines in a class of engineering drawings. - Yuhong Yu; Ashok Samal; Sharad C. Seth (Pattern Recognit., 1994)

HGA: A Hardware-Based Genetic Algorithm. - Stephen D. Scott 001; Ashok Samal; Sharad C. Seth (FPGA, 1995)

A trainable, single-pass algorithm for column segmentation. - Don Sylwester; Sharad C. Seth (ICDAR, 1995)

Parallel test generation with low communication overhead. - Sivaramakrishnan Venkatraman; Sharad C. Seth; Prathima Agrawal (VLSI Design, 1995)

Programming pipelined CAD applications on message-passing architectures. - Paul Kenyon; Sharad C. Seth; Andrea Clematis; Prathima Agrawal; Gabriella Dodero; Vittoria Gianuzzi (Concurr. Pract. Exp., 1995)

Conference Reports. - N. Ranganathan; Sharad C. Seth (IEEE Des. Test Comput., 1995)

A switch-level test generation system for synchronous and asynchronous circuits. - Kent L. Einspahr; Sharad C. Seth (J. Electron. Test., 1995)

Improving Circuit Testability by Clock Control. - Kent L. Einspahr; Sharad C. Seth; Vishwani D. Agrawal (Great Lakes Symposium on VLSI, 1996)

A Prototype for Adaptive Association of Street Names with Streets on Maps. - George Nagy; Ashok Samal; Sharad C. Seth; T. Fisher; E. Guthmann; K. Kalafala; Luyang Li; Prateek Sarkar; S. Sivasubramaniam; Yihong Xu (GREC, 1997)

Synthesis for Testability by Two-Clock Control. - Shashank K. Mehta; Kent L. Einspahr; Sharad C. Seth (VLSI Design, 1997)

A system for recognizing a large class of engineering drawings. - Yuhong Yu; Ashok Samal; Sharad C. Seth (IEEE Trans. Pattern Anal. Mach. Intell., 1997)

Synthesis of Sequential Circuits with Clock Control to Improve Testability. - Kent L. Einspahr; Shashank K. Mehta; Sharad C. Seth (Asian Test Symposium, 1998)

Mutually Disjoint Signals and Probability Calculation in Digital Circuits. - Vishwani D. Agrawal; Sharad C. Seth (Great Lakes Symposium on VLSI, 1998)

Cooperative Text and Line-Art Extraction from a Topographic Map. - Luyang Li; George Nagy; Ashok Samal; Sharad C. Seth; Yihong Xu (ICDAR, 1999)

Empirical Computation of Reject Ratio in VLSI Testing. - Shashank K. Mehta; Sharad C. Seth (VLSI Design, 1999)

A synthesis for testability scheme for finite state machines using clock control. - Kent L. Einspahr; Shashank K. Mehta; Sharad C. Seth (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Exploiting don't cares to enhance functional tests. - Mark W. Weiss; Sharad C. Seth; Shashank K. Mehta; Kent L. Einspahr (ITC, 2000)

Integrated text and line-art extraction from a topographic map. - Luyang Li; George Nagy; Ashok Samal; Sharad C. Seth; Yihong Xu (Int. J. Document Anal. Recognit., 2000)

Adaptive Segmentation of Document Images. - Don Sylwester; Sharad C. Seth (ICDAR, 2001)

Design Verification and Functional Testing of FiniteState Machines. - Mark W. Weiss; Sharad C. Seth; Shashank K. Mehta; Kent L. Einspahr (VLSI Design, 2001)

A Novel Method to Improve the Test Efficiency of VLSI Tests. - Hailong Cui; Sharad C. Seth; Shashank K. Mehta (ASP-DAC/VLSI Design, 2002)

Indirect Symbolic Correlation Approach to Unsegmented Text Recognition. - George Nagy; Sharad C. Seth; Shashank K. Mehta; Yu Lin (CVPR Workshops, 2003)

Double-Tree Scan: A Novel Low-Power Scan-Path Architecture. - Bhargab B. Bhattacharya; Sharad C. Seth; Sheng Zhang 008 (ITC, 2003)

Low-Energy BIST Design for Scan-based Logic Circuits. - Bhargab B. Bhattacharya; Sharad C. Seth; Sheng Zhang 008 (VLSI Design, 2003)

Modeling Fault Coverage of Random Test Patterns. - Hailong Cui; Sharad C. Seth; Shashank K. Mehta (J. Electron. Test., 2003)

A nonparametric classifier for unsegmented text. - George Nagy; Ashutosh Joshi; Mukkai S. Krishnamoorthy; Yu Lin; Daniel P. Lopresti; Shashank K. Mehta; Sharad C. Seth (DRR, 2004)

A feature-based approach to conflation of geospatial sources. - Ashok Samal; Sharad C. Seth; Kevin Cueto (Int. J. Geogr. Inf. Sci., 2004)

Efficient Test Compaction for Pseudo-Random Testing. - Sheng Zhang 008; Sharad C. Seth; Bhargab B. Bhattacharya (Asian Test Symposium, 2005)

On Finding Consecutive Test Vectors in a Random Sequence for Energy-Aware BIST Design. - Sheng Zhang 008; Sharad C. Seth; Bhargab B. Bhattacharya (VLSI Design, 2005)

A Maximum-Likelihood Approach to Symbolic Indirect Correlation. - Ashutosh Joshi; George Nagy; Daniel P. Lopresti; Sharad C. Seth (ICPR (3), 2006)

Multi-character Field Recognition for Arabic and Chinese Handwriting. - Daniel P. Lopresti; George Nagy; Sharad C. Seth; Xiaoli Zhang (SACH, 2006)

Symbolic Path Sensitization Analysis and Applications. - Jian Kang; Sharad C. Seth; Shashank K. Mehta (ATS, 2007)

Efficient RTL Coverage Metric for Functional Test Selection. - Jian Kang; Sharad C. Seth; Vijay Gangaram (VTS, 2007)

Efficient Selection of Observation Points for Functional Tests. - Jian Kang; Sharad C. Seth; Yi-Shing Chang; Vijay Gangaram (ISQED, 2008)

Planar Straight-Line Embedding of Double-Tree Scan Architecture on a Rectangular Grid. - Indranil Saha; Bhargab B. Bhattacharya; Sheng Zhang 008; Sharad C. Seth (Fundam. Informaticae, 2008)

Feature Extraction, Abstract. - Ashok Samal; Sharad C. Seth (Encyclopedia of GIS, 2008)

Conflation of Features. - Sharad C. Seth; Ashok Samal (Encyclopedia of GIS, 2008)

Interactive Conversion of Web Tables. - Raghav Krishna Padmanabhan; Ramana Chakradhar Jandhyala; Mukkai S. Krishnamoorthy; George Nagy; Sharad C. Seth; William Silversmith (GREC, 2009)

From Tessellations to Table Interpretation. - Ramana Chakradhar Jandhyala; Mukkai S. Krishnamoorthy; George Nagy; Raghav K. Padmanabhan; Sharad C. Seth; William Silversmith (Calculemus/MKM, 2009)

Comment: Projection Methods Require Black Border Removal. - George Nagy; Sharad C. Seth; Mahesh Viswanathan 002 (IEEE Trans. Pattern Anal. Mach. Intell., 2009)

Analysis and taxonomy of column header categories for web tables. - Sharad C. Seth; Ramana Chakradhar Jandhyala; Mukkai S. Krishnamoorthy; George Nagy (Document Analysis Systems, 2010)

Exploiting set-level non-uniformity of capacity demand to enhance CMP cooperative caching. - Dongyuan Zhan; Hong Jiang 001; Sharad C. Seth (IPDPS, 2010)

Hardware implementation of the double-tree scan architecture. - Nathan Schemm; Sina Balkir; Sharad C. Seth (ISCAS, 2010)

STEM: Spatiotemporal Management of Capacity for Intra-core Last Level Caches. - Dongyuan Zhan; Hong Jiang 001; Sharad C. Seth (MICRO, 2010)

A Unified Solution to Scan Test Volume, Time, and Power Minimization. - Zhen Chen; Sharad C. Seth; Dong Xiang; Bhargab B. Bhattacharya (VLSI Design, 2010)

A novel hybrid delay testing scheme with low test power, volume, and time. - Zhen Chen; Sharad C. Seth; Dong Xiang (VTS, 2010)

PVT: Unified Reduction of Test Power, Volume, and Test Time Using Double-Tree Scan Architecture. - Zhen Chen; Sharad C. Seth; Dong Xiang; Bhargab B. Bhattacharya (J. Low Power Electron., 2010)

Diagnosis of Multiple Scan-Chain Faults in the Presence of System Logic Defects. - Zhen Chen; Sharad C. Seth; Dong Xiang; Bhargab B. Bhattacharya (Asian Test Symposium, 2011)

Data Extraction from Web Tables: The Devil is in the Details. - George Nagy; Sharad C. Seth; Dongpu Jin; David W. Embley; Spencer Machado; Mukkai S. Krishnamoorthy (ICDAR, 2011)

Factoring Web Tables. - David W. Embley; Mukkai S. Krishnamoorthy; George Nagy; Sharad C. Seth (IEA/AIE (1), 2011)

Locality & utility co-optimization for practical capacity management of shared last level caches. - Dongyuan Zhan; Hong Jiang 001; Sharad C. Seth (ICS, 2012)

Segmenting Tables via Indexing of Value Cells by Table Headers. - Sharad C. Seth; George Nagy (ICDAR, 2013)

End-to-End Conversion of HTML Tables for Populating a Relational Database. - George Nagy; Sharad C. Seth; David W. Embley (Document Analysis Systems, 2014)

Transforming Web Tables to a Relational Database. - David W. Embley; Sharad C. Seth; George Nagy (ICPR, 2014)

CLU: Co-Optimizing Locality and Utility in Thread-Aware Capacity Management for Shared Last Level Caches. - Dongyuan Zhan; Hong Jiang 001; Sharad C. Seth (IEEE Trans. Computers, 2014)

Clustering header categories extracted from web tables. - George Nagy; David W. Embley; Mukkai S. Krishnamoorthy; Sharad C. Seth (DRR, 2015)

Factors affecting scalability of multithreaded Java applications on manycore systems. - Junjie Qian; Du Li; Witawas Srisa-an; Hong Jiang 001; Sharad C. Seth (ISPASS, 2015)

SmartStealing: Analysis and Optimization of Work Stealing in Parallel Garbage Collection for Java VM. - Junjie Qian; Witawas Srisa-an; Du Li; Hong Jiang 001; Sharad C. Seth; Yaodong Yang 003 (PPPJ, 2015)

Table headers: An entrance to the data mine. - George Nagy; Sharad C. Seth (ICPR, 2016)

Exploiting FIFO Scheduler to Improve Parallel Garbage Collection Performance. - Junjie Qian; Witawas Srisa-an; Sharad C. Seth; Hong Jiang 001; Du Li; Pan Yi (VEE, 2016)

Converting heterogeneous statistical tables on the web to searchable databases. - David W. Embley; Mukkai S. Krishnamoorthy; George Nagy; Sharad C. Seth (Int. J. Document Anal. Recognit., 2016)

Energy-efficient I/O Thread Schedulers for NVMe SSDs on NUMA. - Junjie Qian; Hong Jiang 001; Witawas Srisa-an; Sharad C. Seth; Stan Skelton; Joseph Moore (CCGrid, 2017)

Feature Extraction, Abstract. - Ashok Samal; Sharad C. Seth (Encyclopedia of GIS, 2017)

Conflation of Features. - Sharad C. Seth; Ashok Samal (Encyclopedia of GIS, 2017)

Leverage Redundancy in Hardware Transactional Memory to Improve Cache Reliability. - Zhichao Yan; Hong Jiang 001; Witawas Srisa-an; Sharad C. Seth; Yujuan Tan (ICPP, 2018)