A 28nm 6T SRAM memory compiler with a variation tolerant replica circuit. - Sharad Gupta; Parvinder Kumar Rana (ISOCC, 2012)

A 40nm 650Mhz 0.5fJ/Bit/Search TCAM Compiler Using Complementary Bit-cell Architecture. - Rashmi Sachan; Shahid Ali; Chandan Bist; Sunil Misra; Vinod Menezes; Sharad Gupta; Pat Bosshart (VLSI Design, 2013)

INNAMP: An incremental neural network architecture with monitor perceptron. - Sharad Gupta; Sudip Sanyal (AI Commun., 2018)

A Real Time Multi-Bit DAC Mismatch Estimation & Correction Technique For Wideband Continuous Time Sigma Delta Modulators. - Ankur Bal; Sharad Gupta; Rupesh Singh (VLSID, 2022)

Electrocardiogram signal pattern recognition using PCA and ICA on different databases for improved health management. - Varun Gupta; Natwar Singh Rathore; Amit Kumar Arora; Sharad Gupta; Abhas Kanungo; Salim; Neeraj Kumar Gupta (Int. J. Appl. Pattern Recognit., 2022)