Logic verification using binary decision diagrams in a logic synthesis environment. - Sharad Malik; Albert R. Wang; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1988)

MIS-MV: Optimization of Multi-Level Logic with Multiple-Valued Inputs. - Luciano Lavagno; Sharad Malik; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1990)

Performance Optimization of Pipelined Circuits. - Sharad Malik; Kanwar Jit Singh; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1990)

Algorithms for Discrete Function Manipulation. - Arvind Srinivasan 004; Timothy Kam; Sharad Malik; Robert K. Brayton (ICCAD, 1990)

Delay Computation in Combinational Logic Circuits: Theory and Algorithms. - Srinivas Devadas; Kurt Keutzer; Sharad Malik (ICCAD, 1991)

Is redundancy necessary to reduce delay? - Kurt Keutzer; Sharad Malik; Alexander Saldanha (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Retiming and resynthesis: optimizing sequential networks with combinational techniques. - Sharad Malik; Ellen M. Sentovich; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Exploiting multi-cycle false paths in the performance optimization of sequential circuits. - Pranav Ashar; Sujit Dey; Sharad Malik (ICCAD, 1992)

Statistical Timing Analysis of Combinational Circuits. - Srinivas Devadas; Horng-Fei Jyu; Kurt Keutzer; Sharad Malik (ICCD, 1992)

Symbolic minimization of multilevel logic and the input encoding problem. - Sharad Malik; Luciano Lavagno; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

Technology Mapping for Lower Power. - Vivek Tiwari; Pranav Ashar; Sharad Malik (DAC, 1993)

Statistical Timing Optimization of Combinatorial Logic Circuits. - Horng-Fei Jyu; Sharad Malik (ICCD, 1993)

A synthesis-based test generation and compaction algorithm for multifaults. - Srinivas Devadas; Kurt Keutzer; Sharad Malik (J. Electron. Test., 1993)

Permutation and phase independent Boolean comparison. - Janett Mohnke; Sharad Malik (Integr., 1993)

Computation of floating mode delay in combinational circuits: theory and algorithms. - Srinivas Devadas; Kurt Keutzer; Sharad Malik (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Computation of floating mode delay in combinational circuits: practice and implementation. - Srinivas Devadas; Kurt Keutzer; Sharad Malik; Albert R. Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Performance optimization of pipelined logic circuits using peripheral retiming and resynthesis. - Sharad Malik; Kanwar Jit Singh; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Statistical timing analysis of combinational logic circuits. - Horng-Fei Jyu; Sharad Malik; Srinivas Devadas; Kurt Keutzer (IEEE Trans. Very Large Scale Integr. Syst., 1993)

Implicit Computation of Minimum-Cost Feedback-Vertex Sets for Partial Scan and Other Applications. - Pranav Ashar; Sharad Malik (DAC, 1994)

Statistical Delay Modeling in Logic Design and Synthesis. - Horng-Fei Jyu; Sharad Malik (DAC, 1994)

Challenges in code generation for embedded processors. - Guido Araujo; Srinivas Devadas; Kurt Keutzer; Stan Y. Liao; Sharad Malik; Ashok Sudarsanam; Steven W. K. Tjiang; Albert R. Wang (Code Generation for Embedded Processors, 1994)

Event suppression: improving the efficiency of timing simulation for synchronous digital circuits. - Srinivas Devadas; Kurt Keutzer; Sharad Malik; Albert R. Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Analysis of cyclic combinational circuits. - Sharad Malik (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Certified timing verification and the transition delay of a logic circuit. - Srinivas Devadas; Kurt Keutzer; Sharad Malik; Albert R. Wang (IEEE Trans. Very Large Scale Integr. Syst., 1994)

Power analysis of embedded software: a first step towards software power minimization. - Vivek Tiwari; Sharad Malik; Andrew Wolfe (IEEE Trans. Very Large Scale Integr. Syst., 1994)

Verification of asynchronous interface circuits with bounded wire delays. - Srinivas Devadas; Kurt Keutzer; Sharad Malik; Albert R. Wang (J. VLSI Signal Process., 1994)

Editorial. - Teresa H. Meng; Sharad Malik (J. VLSI Signal Process., 1994)

A Survey of Optimization Techniques Targeting Low Power VLSI Circuits. - Srinivas Devadas; Sharad Malik (DAC, 1995)

Prediction of interconnect delay in logic synthesis. - Horng-Fei Jyu; Sharad Malik (ED&TC, 1995)

Fast functional simulation using branching programs. - Pranav Ashar; Sharad Malik (ICCAD, 1995)

Memory bank and register allocation in software synthesis for ASIPs. - Ashok Sudarsanam; Sharad Malik (ICCAD, 1995)

Optimal code generation for embedded memory non-homogeneous register architectures. - Guido Araujo; Sharad Malik (ISSS, 1995)

Power analysis and low-power scheduling techniques for embedded DSP software. - Mike Tien-Chien Lee; Vivek Tiwari; Sharad Malik; Masahiro Fujita (ISSS, 1995)

Efficient Microarchitecture Modeling and Path Analysis for Real-Time Software. - Yau-Tsun Steven Li; Sharad Malik; Andrew Wolfe (RTSS, 1995)

Multisensor Integration for Underwater Scene Classification. - N. Nandhakumar; Sharad Malik (Appl. Intell., 1995)

Exploiting multicycle false paths in the performance optimization of sequential logic circuits. - Pranav Ashar; Sujit Dey; Sharad Malik (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Functional timing analysis using ATPG. - Pranav Ashar; Sharad Malik (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Test generation for cyclic combinational circuits. - Anand Raghunathan; Pranav Ashar; Sharad Malik (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Using Register-Transfer Paths in Code Generation for Heterogeneous Memory-Register Architectures. - Guido Araujo; Sharad Malik; Mike Tien-Chien Lee (DAC, 1996)

The case for retiming with explicit reset circuitry. - Vigyan Singhal; Sharad Malik; Robert K. Brayton (ICCAD, 1996)

Instruction Set Design and Optimizations for Address Computation in DSP Architectures. - Guido Araujo; Ashok Sudarsanam; Sharad Malik (ISSS, 1996)

Cache modeling for real-time software: beyond direct mapped instruction caches. - Yau-Tsun Steven Li; Sharad Malik; Andrew Wolfe (RTSS, 1996)

Register Transfer Level Synthesis: From Theory to Practice. - Kurt Keutzer; Sharad Malik (VLSI Design, 1996)

Technology mapping for low power in logic synthesis. - Vivek Tiwari; Pranav Ashar; Sharad Malik (Integr., 1996)

Instruction level power analysis and optimization of software. - Vivek Tiwari; Sharad Malik; Andrew Wolfe; Mike Tien-Chien Lee (J. VLSI Signal Process., 1996)

Toward Formalizing a Validation Methodology Using Simulation Coverage. - Aarti Gupta; Sharad Malik; Pranav Ashar (DAC, 1997)

Static Timing Analysis of Embedded Software. - Sharad Malik; Margaret Martonosi; Yau-Tsun Steven Li (DAC, 1997)

Cinderella: A Retargetable Environment for Performance Analysis of Real-Time Software. - Yau-Tsun Steven Li; Sharad Malik; Andrew Wolfe (Euro-Par, 1997)

Optimization of embedded DSP programs using post-pass data-flow analysis. - Ashok Sudarsanam; Sharad Malik; Steven W. K. Tjiang; Stan Y. Liao (ICASSP, 1997)

Cache Miss Equations: An Analytical Representation of Cache Misses. - Somnath Ghosh; Margaret Martonosi; Sharad Malik (International Conference on Supercomputing, 1997)

Dynamic Power Management for Microprocessors: A Case Study. - Vivek Tiwari; Ryan Donnelly; Sharad Malik; Ricardo Gonzalez (VLSI Design, 1997)

Delay abstraction in combinational logic circuits. - Noriya Kobayashi; Sharad Malik (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Performance analysis of embedded software using implicit path enumeration. - Yau-Tsun Steven Li; Sharad Malik (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Power analysis and minimization techniques for embedded DSP software. - Mike Tien-Chien Lee; Vivek Tiwari; Sharad Malik; Masahiro Fujita (IEEE Trans. Very Large Scale Integr. Syst., 1997)

Precise Miss Analysis for Program Transformations with Caches of Arbitrary Associativity. - Somnath Ghosh; Margaret Martonosi; Sharad Malik (ASPLOS, 1998)

Using Reconfigurable Computing Techniques to Accelerate Problems in the CAD Domain: A Case Study with Boolean Satisfiability. - Peixin Zhong; Pranav Ashar; Sharad Malik; Margaret Martonosi (DAC, 1998)

Accelerating Boolean Satisfiability with Configurable Hardware. - Peixin Zhong; Margaret Martonosi; Pranav Ashar; Sharad Malik (FCCM, 1998)

Solving Boolean Satisfiability with Dynamic Hardware Configurations. - Peixin Zhong; Margaret Martonosi; Pranav Ashar; Sharad Malik (FPL, 1998)

Guarded evaluation: pushing power management to logic synthesis/design. - Vivek Tiwari; Sharad Malik; Pranav Ashar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

Code generation for fixed-point DSPs. - Guido Araujo; Sharad Malik (ACM Trans. Design Autom. Electr. Syst., 1998)

Performance analysis of real-time embedded software. - Yau-Tsun Steven Li; Sharad Malik (Springer, 1999)

Exploiting Retiming in a Guided Simulation Based Validation Methodology. - Aarti Gupta; Pranav Ashar; Sharad Malik (CHARME, 1999)

Development of an optimizing compiler for a Fujitsu fixed-point digital signal processor. - Sreeranga P. Rajan; Masahiro Fujita; Ashok Sudarsanam; Sharad Malik (CODES, 1999)

Exact Memory Size Estimation for Array Computations without Loop Unrolling. - Ying Zhao; Sharad Malik (DAC, 1999)

CAD Techniques for Embedded System Design. - Srinivas Devadas; Sharad Malik; José Monteiro 001; Luciano Lavagno (VLSI Design, 1999)

A Retargetable Compilation Methodology for Embedded Digital Signal Processors Using a Machine-Dependent Code Optimization Library. - Ashok Sudarsanam; Sharad Malik; Masahiro Fujita (Des. Autom. Embed. Syst., 1999)

Paged Absolute Addressing Mode Optimizations for Embedded Digital Signal Processors Using Post-pass Data-flow Analysis. - Ashok Sudarsanam; Sharad Malik; Steven W. K. Tjiang; Stan Y. Liao (Des. Autom. Embed. Syst., 1999)

Establishing latch correspondence for sequential circuits using distinguishing signatures. - Janett Mohnke; Paul Molitor; Sharad Malik (Integr., 1999)

Using configurable computing to accelerate Boolean satisfiability. - Peixin Zhong; Margaret Martonosi; Pranav Ashar; Sharad Malik (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Performance estimation of embedded software with instruction cache modeling. - Yau-Tsun Steven Li; Sharad Malik; Andrew Wolfe (ACM Trans. Design Autom. Electr. Syst., 1999)

Cache miss equations: a compiler framework for analyzing and tuning memory behavior. - Somnath Ghosh; Margaret Martonosi; Sharad Malik (ACM Trans. Program. Lang. Syst., 1999)

Handling irregular ILP within conventional VLIW schedulers using artificial resource constraints. - Subramanian Rajagopalan; Manish Vachharajani; Sharad Malik (CASES, 2000)

Embedded systems education (panel abstract). - Sharad Malik; D. K. Arvind 001; Edward A. Lee; Phil Koopman; Alberto L. Sangiovanni-Vincentelli; Wayne H. Wolf (DAC, 2000)

Incremental CAD. - Olivier Coudert; Jason Cong; Sharad Malik; Majid Sarrafzadeh (ICCAD, 2000)

Automated cache optimizations using CME driven diagnosis. - Somnath Ghosh; Margaret Martonosi; Sharad Malik (ICS, 2000)

Processor Evaluation in an Embedded Systems Design Environment. - T. Vinod Kumar Gupta; Purvesh Sharma; M. Balakrishnan; Sharad Malik (VLSI Design, 2000)

Simultaneous reference allocation in code generation for dual data memory bank ASIPs. - Ashok Sudarsanam; Sharad Malik (ACM Trans. Design Autom. Electr. Syst., 2000)

Exact memory size estimation for array computations. - Ying Zhao; Sharad Malik (IEEE Trans. Very Large Scale Integr. Syst., 2000)

Optimal Live Range Merge for Address Register Allocation in Embedded Programs. - Guilherme Ottoni; Sandro Rigo; Guido Araujo; Subramanian Rajagopalan; Sharad Malik (CC, 2001)

Chaff: Engineering an Efficient SAT Solver. - Matthew W. Moskewicz; Conor F. Madigan; Ying Zhao; Lintao Zhang; Sharad Malik (DAC, 2001)

Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design. - Marco Sgroi; Michael Sheets; Andrew Mihal; Kurt Keutzer; Sharad Malik; Jan M. Rabaey; Alberto L. Sangiovanni-Vincentelli (DAC, 2001)

Managing dynamic reconfiguration overhead in systems-on-a-chip design using reconfigurable datapaths and optimized interconnection networks. - Zhining Huang; Sharad Malik (DATE, 2001)

Embedded Software Implementation Tools for Fully Programmable Application Specific Systems. - Sharad Malik (EMSOFT, 2001)

Partition-Based Decision Heuristics for Image Computation Using SAT and BDDs. - Aarti Gupta; Zijiang Yang 006; Pranav Ashar; Lintao Zhang; Sharad Malik (ICCAD, 2001)

Efficient Conflict Driven Learning in Boolean Satisfiability Solver. - Lintao Zhang; Conor F. Madigan; Matthew W. Moskewicz; Sharad Malik (ICCAD, 2001)

Matching Architecture to Application Via Configurable Processors: A Case Study with Boolean Satisfiability Problem. - Ying Zhao; Sharad Malik; Albert R. Wang; Matthew W. Moskewicz; Conor F. Madigan (ICCD, 2001)

Retargetable static timing analysis for embedded software. - Kaiyu Chen; Sharad Malik; David I. August (ISSS, 2001)

Accelerating boolean satisfiability through application specific processing. - Ying Zhao; Sharad Malik; Matthew W. Moskewicz; Conor F. Madigan (ISSS, 2001)

Application of BDDs in Boolean matching techniques for formal logic combinational verification. - Janett Mohnke; Paul Molitor; Sharad Malik (Int. J. Softw. Tools Technol. Transf., 2001)

A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism. - Subramanian Rajagopalan; Sreeranga P. Rajan; Sharad Malik; Sandro Rigo; Guido Araujo; Koichiro Takayama (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Using complete-1-distinguishability for FSM equivalence checking. - Pranav Ashar; Aarti Gupta; Sharad Malik (ACM Trans. Design Autom. Electr. Syst., 2001)

Architecture Description Languages for Retargetable Compilation. - Wei Qin; Sharad Malik (The Compiler Design Handbook, 2002)

Retargetable Very Long Instuction Word Compiler Framework for Digital Signal Processors. - Subramanian Rajagopalan; Sharad Malik (The Compiler Design Handbook, 2002)

The Quest for Efficient Boolean Satisfiability Solvers. - Lintao Zhang; Sharad Malik (CAV, 2002)

Towards a Symmetric Treatment of Satisfaction and Conflicts in Quantified Boolean Formula Evaluation. - Lintao Zhang; Sharad Malik (CP, 2002)

Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver. - Malay K. Ganai; Pranav Ashar; Aarti Gupta; Lintao Zhang; Sharad Malik (DAC, 2002)

Exploiting operation level parallelism through dynamically reconfigurable datapaths. - Zhining Huang; Sharad Malik (DAC, 2002)

Unified tools for SoC embedded systems: mission critical, mission impossible or mission irrelevant? - Gary Smith 001; Daya Nadamuni; Sharad Malik; Rick Chapman; John Fogelin; Kurt Keutzer; Grant Martin; Brian Bailey (DAC, 2002)

Design Tools for Application Specific Embedded Processors. - Wei Qin; Subramanian Rajagopalan; Manish Vachharajani; Hangsheng Wang; Xinping Zhu; David I. August; Kurt Keutzer; Sharad Malik; Li-Shiuan Peh (EMSOFT, 2002)

Conflict driven learning in a quantified Boolean Satisfiability solver. - Lintao Zhang; Sharad Malik (ICCAD, 2002)

A hierarchical modeling framework for on-chip communication architectures. - Xinping Zhu; Sharad Malik (ICCAD, 2002)

From ASIC to ASIP: The Next Design Discontinuity. - Kurt Keutzer; Sharad Malik; A. Richard Newton (ICCD, 2002)

Datapath Merging and Interconnection Sharing for Reconfigurable Architectures. - Guido Araujo; Sharad Malik; Zhining Huang; Nahri Moreano (ISSS, 2002)

Orion: a power-performance simulator for interconnection networks. - Hangsheng Wang; Xinping Zhu; Li-Shiuan Peh; Sharad Malik (MICRO, 2002)

Developing Architectural Platforms: A Disciplined Approach. - Andrew Mihal; Chidamber Kulkarni; Matthew W. Moskewicz; Mel M. Tsai; Niraj Shah; Scott J. Weber; Yujia Jin; Kurt Keutzer; Christian Sauer 001; Kees A. Vissers; Sharad Malik (IEEE Des. Test Comput., 2002)

Limits of Using Signatures for Permutation Independent Boolean Comparison. - Janett Mohnke; Paul Molitor; Sharad Malik (Formal Methods Syst. Des., 2002)

Modeling and Integration of Peripheral Devices in Embedded Systems. - Shaojie Wang; Sharad Malik; Reinaldo A. Bergamaschi (Embedded Software for SoC, 2003)

Synthesizing operating system based device drivers in embedded systems. - Shaojie Wang; Sharad Malik (CODES+ISSS, 2003)

Automated synthesis of efficient binary decoders for retargetable software toolkits. - Wei Qin; Sharad Malik (DAC, 2003)

Flexible and Formal Modeling of Microprocessors with Application to Retargetable Simulation. - Wei Qin; Sharad Malik (DATE, 2003)

Modeling and Integration of Peripheral Devices in Embedded Systems. - Shaojie Wang; Sharad Malik; Reinaldo A. Bergamaschi (DATE, 2003)

Validating SAT Solvers Using an Independent Resolution-Based Checker: Practical Implementations and Other Applications. - Lintao Zhang; Sharad Malik (DATE, 2003)

Power-driven Design of Router Microarchitectures in On-chip Networks. - Hangsheng Wang; Li-Shiuan Peh; Sharad Malik (MICRO, 2003)

Compile-time dynamic voltage scaling settings: opportunities and limits. - Fen Xie; Margaret Martonosi; Sharad Malik (PLDI, 2003)

Cache Performance of SAT Solvers: a Case Study for Efficient Implementation of Algorithms. - Lintao Zhang; Sharad Malik (SAT, 2003)

A Power Model for Routers: Modeling Alpha 21364 and InfiniBand Routers. - Hangsheng Wang; Li-Shiuan Peh; Sharad Malik (IEEE Micro, 2003)

Facilitating reuse in hardware models with enhanced type inference. - Manish Vachharajani; Neil Vachharajani; Sharad Malik; David I. August (CODES+ISSS, 2004)

Using a Communication Architecture Specification in an Application-Driven Retargetable Prototyping Platform for Multiprocessing. - Xinping Zhu; Sharad Malik (DATE, 2004)

Achieving Structural and Composable Modeling of Complex Systems. - David I. August; Sharad Malik; Li-Shiuan Peh; Vijay S. Pai (IPDPS Next Generation Software Program - NSFNGS - PI Workshop, 2004)

A formal concurrency model based architecture description language for synthesis of software development tools. - Wei Qin; Subramanian Rajagopalan; Sharad Malik (LCTES, 2004)

Zchaff2004: An Efficient SAT Solver. - Yogesh S. Mahajan; Zhaohui Fu; Sharad Malik (SAT (Selected Papers, 2004)

A Comparative Study of 2QBF Algorithms. - Darsh Ranjan; Daijue Tang; Sharad Malik (SAT, 2004)

Analysis of Search Based Algorithms for Satisfiability of Quantified Boolean Formulas Arising from Circuit State Space Diameter Problems. - Daijue Tang; Yinlei Yu; Darsh Ranjan; Sharad Malik (SAT, 2004)

Analysis of Search Based Algorithms for Satisfiability of Propositional and Quantified Boolean Formulas Arising from Circuit State Space Diameter Problems. - Daijue Tang; Yinlei Yu; Darsh Ranjan; Sharad Malik (SAT (Selected Papers, 2004)

Guest Editors' Introduction: Exploring Synergies for Design Verification. - Carl Pixley; Sharad Malik (IEEE Des. Test Comput., 2004)

Intraprogram dynamic voltage scaling: Bounding opportunities with analytic modeling. - Fen Xie; Margaret Martonosi; Sharad Malik (ACM Trans. Archit. Code Optim., 2004)

The design of dynamically reconfigurable datapath coprocessors. - Zhining Huang; Sharad Malik; Nahri Moreano; Guido Araujo (ACM Trans. Embed. Comput. Syst., 2004)

Validating the result of a Quantified Boolean Formula (QBF) solver: theory and practice. - Yinlei Yu; Sharad Malik (ASP-DAC, 2005)

Symmetry Reduction in SAT-Based Model Checking. - Daijue Tang; Sharad Malik; Aarti Gupta; C. Norris Ip (CAV, 2005)

Efficient behavior-driven runtime dynamic voltage scaling policies. - Fen Xie; Margaret Martonosi; Sharad Malik (CODES+ISSS, 2005)

Considering Circuit Observability Don't Cares in CNF Satisfiability. - Zhaohui Fu; Yinlei Yu; Sharad Malik (DATE, 2005)

A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks. - Hangsheng Wang; Li-Shiuan Peh; Sharad Malik (DATE, 2005)

A Case for Runtime Validation of Hardware. - Sharad Malik (Haifa Verification Conference, 2005)

Complementary use of runtime validation and model checking. - Ali Alphan Bayazit; Sharad Malik (ICCAD, 2005)

Bounds on power savings using runtime dynamic voltage scaling: an exact algorithm and a linear-time heuristic approximation. - Fen Xie; Margaret Martonosi; Sharad Malik (ISLPED, 2005)

A Study of Architecture Description Languages from a Model-based Perspective. - Wei Qin; Sharad Malik (MTV, 2005)

Achieving Structural and Composable Modeling of Complex Systems. - David I. August; Sharad Malik; Li-Shiuan Peh; Vijay S. Pai; Manish Vachharajani; Paul Willmann (Int. J. Parallel Program., 2005)

Understanding the Dynamic Behavior of Modern DPLL SAT Solvers through Visual Analysis. - Cameron Brien; Sharad Malik (FMCAD, 2006)

Solving the minimum-cost satisfiability problem using SAT based branch-and-bound search. - Zhaohui Fu; Sharad Malik (ICCAD, 2006)

Dependable Multithreaded Processing Using Runtime Validation. - Kaiyu Chen; Sharad Malik (PRDC, 2006)

On Solving the Partial MAX-SAT Problem. - Zhaohui Fu; Sharad Malik (SAT, 2006)

Solving Quantified Boolean Formulas with Circuit Observability Don't Cares. - Daijue Tang; Sharad Malik (SAT, 2006)

Lemma Learning in SMT on Linear Constraints. - Yinlei Yu; Sharad Malik (SAT, 2006)

The Liberty Simulation Environment: A deliberate approach to high-level system modeling. - Manish Vachharajani; Neil Vachharajani; David A. Penry; Jason A. Blome; Sharad Malik; David I. August (ACM Trans. Comput. Syst., 2006)

Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation. - Xinping Zhu; Wei Qin; Sharad Malik (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Architecture Description Languages for Retargetable Compilation. - Wei Qin; Sharad Malik (The Compiler Design Handbook, 2nd ed., 2007)

A Retargetable Very Long Instruction Word Compiler Framework for Digital Signal Processors. - Subramanian Rajagopalan; Sharad Malik (The Compiler Design Handbook, 2nd ed., 2007)

Automating Hazard Checking in Transaction-Level Microarchitecture Models. - Yogesh S. Mahajan; Sharad Malik (FMCAD, 2007)

Verification Driven Formal Architecture and Microarchitecture Modeling. - Yogesh S. Mahajan; Carven Chan; Ali Alphan Bayazit; Sharad Malik; Wei Qin (MEMOCODE, 2007)

Extracting Logic Circuit Structure from Conjunctive Normal Form Descriptions. - Zhaohui Fu; Sharad Malik (VLSI Design, 2007)

A hierarchical modeling framework for on-chip communication architectures of multiprocessing SoCs. - Xinping Zhu; Sharad Malik (ACM Trans. Design Autom. Electr. Syst., 2007)

Runtime validation of memory ordering using constraint graph checking. - Kaiyu Chen; Sharad Malik; Priyadarsan Patra (HPCA, 2008)

Runtime Validation of Transactional Memory Systems. - Kaiyu Chen; Sharad Malik; Priyadarsan Patra (ISQED, 2008)

Hardware Verification: Techniques, Methodology and Solutions. - Sharad Malik (TACAS, 2008)

Exploiting Circuit Reconvergence through Static Learning in CNF SAT Solvers. - Yinlei Yu; Cameron Brien; Sharad Malik (VLSI Design, 2008)

Challenges and Solutions for Late- and Post-Silicon Design. - Jan M. Rabaey; Sharad Malik (IEEE Des. Test Comput., 2008)

Declarative Infrastructure Configuration Synthesis and Debugging. - Sanjai Narain; Gary Levin; Sharad Malik; Vikram Kaul (J. Netw. Syst. Manag., 2008)

Supporting RTL flow compatibility in a microarchitecture-level design framework. - Daniel Schwartz-Narbonne; Carven Chan; Yogesh S. Mahajan; Sharad Malik (CODES+ISSS, 2009)

Boolean satisfiability from theoretical hardness to practical success. - Sharad Malik; Lintao Zhang (Commun. ACM, 2009)

Preface. - Aarti Gupta; Sharad Malik (Formal Methods Syst. Des., 2009)

Conflict-Driven Clause Learning SAT Solvers. - João Marques-Silva 001; Inês Lynce; Sharad Malik (Handbook of Satisfiability, 2009)

Utility of transaction-level hardware models in refinement checking. - Yogesh S. Mahajan; Sharad Malik (HLDVT, 2010)

Runtime checking of serializability in software transactional memory. - Arnab Sinha 001; Sharad Malik (IPDPS, 2010)

Post-silicon fault localisation using maximum satisfiability and backbones. - Charlie Shucheng Zhu; Georg Weissenbacher; Sharad Malik (FMCAD, 2011)

SAT-based techniques for determining backbones for post-silicon fault localisation. - Charlie Shucheng Zhu; Georg Weissenbacher; Divjyot Sethi; Sharad Malik (HLDVT, 2011)

Predicting Serializability Violations: SMT-Based Search vs. DPOR-Based Search. - Arnab Sinha 001; Sharad Malik; Chao Wang 001; Aarti Gupta (Haifa Verification Conference, 2011)

Parallel assertions for debugging parallel programs. - Daniel Schwartz-Narbonne; Feng Liu; Tarun Pondicherry; David I. August; Sharad Malik (MEMOCODE, 2011)

Predictive analysis for detecting serializability violations through Trace Segmentation. - Arnab Sinha 001; Sharad Malik; Chao Wang 001; Aarti Gupta (MEMOCODE, 2011)

Runtime Verification: A Computer Architecture Perspective. - Sharad Malik (RV, 2011)

Towards Eliminating Configuration Errors in Cyber Infrastructure. - Sanjai Narain; Sharad Malik; Ehab Al-Shaer (SafeConfig, 2011)

Specification and encoding of transaction interaction properties. - Divjyot Sethi; Yogesh S. Mahajan; Sharad Malik (Formal Methods Syst. Des., 2011)

EPROF: An energy/performance/reliability optimization framework for streaming applications. - Yavuz Yetim; Sharad Malik; Margaret Martonosi (ASP-DAC, 2012)

Parallel Assertions for Architectures with Weak Memory Models. - Daniel Schwartz-Narbonne; Georg Weissenbacher; Sharad Malik (ATVA, 2012)

Verification of Computer Switching Networks: An Overview. - Shuyuan Zhang; Sharad Malik; Rick McGeer (ATVA, 2012)

passert: A Tool for Debugging Parallel Programs. - Daniel Schwartz-Narbonne; Feng Liu; David I. August; Sharad Malik (CAV, 2012)

Specification and synthesis of hardware checkpointing and rollback mechanisms. - Carven Chan; Daniel Schwartz-Narbonne; Divjyot Sethi; Sharad Malik (DAC, 2012)

Efficient predictive analysis for detecting nondeterminism in multi-threaded programs. - Arnab Sinha 001; Sharad Malik; Aarti Gupta (FMCAD, 2012)

Coverage-Based Trace Signal Selection for Fault Localisation in Post-silicon Validation. - Charlie Shucheng Zhu; Georg Weissenbacher; Sharad Malik (Haifa Verification Conference, 2012)

Verification and synthesis of firewalls using SAT and QBF. - Shuyuan Zhang; Abdulrahman Mahmoud; Sharad Malik; Sanjai Narain (ICNP, 2012)

Parameterized Model Checking of Fine Grained Concurrency. - Divjyot Sethi; Muralidhar Talupur; Daniel Schwartz-Narbonne; Sharad Malik (SPIN, 2012)

Wolverine: Battling Bugs with Interpolants - (Competition Contribution). - Georg Weissenbacher; Daniel Kroening; Sharad Malik (TACAS, 2012)

Boolean Satisfiability Solvers: Techniques and Extensions. - Georg Weissenbacher; Sharad Malik (Software Safety and Security, 2012)

SAT Based Verification of Network Data Planes. - Shuyuan Zhang; Sharad Malik (ATVA, 2013)

Reverse engineering digital circuits using functional analysis. - Pramod Subramanyan; Nestan Tsiskaridze; Kanika Pasricha; Dillon Reisman; Adriana Susnea; Sharad Malik (DATE, 2013)

Extracting useful computation from error-prone processors for streaming applications. - Yavuz Yetim; Margaret Martonosi; Sharad Malik (DATE, 2013)

Abstractions for model checking SDN controllers. - Divjyot Sethi; Srinivas Narayana; Sharad Malik (FMCAD, 2013)

WordRev: Finding word-level structures in a sea of bit-level gates. - Wenchao Li 001; Adrià Gascón; Pramod Subramanyan; Wei Yang Tan; Ashish Tiwari 001; Sharad Malik; Natarajan Shankar; Sanjit A. Seshia (HOST, 2013)

Modeling Firmware as Service Functions and Its Application to Test Generation. - Sunha Ahn; Sharad Malik (Haifa Verification Conference, 2013)

Using Flow Specifications of Parameterized Cache Coherence Protocols for Verifying Deadlock Freedom. - Divjyot Sethi; Muralidhar Talupur; Sharad Malik (ATVA, 2014)

Automated firmware testing using firmware-hardware interaction patterns. - Sunha Ahn; Sharad Malik (CODES+ISSS, 2014)

An Adaptable Rule Placement for Software-Defined Networks. - Shuyuan Zhang; Franjo Ivancic; Cristian Lumezanu; Yifei Yuan 001; Aarti Gupta; Sharad Malik (DSN, 2014)

Template-based circuit understanding. - Adrià Gascón; Pramod Subramanyan; Bruno Dutertre; Ashish Tiwari 001; Dejan Jovanovic; Sharad Malik (FMCAD, 2014)

Reduction of Resolution Refutations and Interpolants via Subsumption. - Roderick Bloem; Sharad Malik; Matthias Schlaipfer; Georg Weissenbacher (Haifa Verification Conference, 2014)

Silicon fault diagnosis using sequence interpolation with backbones. - Charlie Shucheng Zhu; Georg Weissenbacher; Sharad Malik (ICCAD, 2014)

In-Band Update for Network Routing Policy Migration. - Shuyuan Zhang; Sharad Malik; Sanjai Narain; Laurent Vanbever (ICNP, 2014)

Effective abstraction for response proof of communication fabrics. - Sayak Ray; Sharad Malik (NOCS, 2014)

An assertion language for debugging SDN applications. - Ryan Beckett; Xuan Kelvin Zou; Shuyuan Zhang; Sharad Malik; Jennifer Rexford; David Walker 001 (HotSDN, 2014)

All-SAT Using Minimal Blocking Clauses. - Yinlei Yu; Pramod Subramanyan; Nestan Tsiskaridze; Sharad Malik (VLSID, 2014)

Reverse Engineering Digital Circuits Using Structural and Functional Analyses. - Pramod Subramanyan; Nestan Tsiskaridze; Wenchao Li 001; Adrià Gascón; Wei Yang Tan; Ashish Tiwari 001; Natarajan Shankar; Sanjit A. Seshia; Sharad Malik (IEEE Trans. Emerg. Top. Comput., 2014)

Boolean Satisfiability: Solvers and Extensions. - Georg Weissenbacher; Pramod Subramanyan; Sharad Malik (Software Systems Safety, 2014)

CommGuard: Mitigating Communication Errors in Error-Prone Parallel Execution. - Yavuz Yetim; Sharad Malik; Margaret Martonosi (ASPLOS, 2015)

Fast Interpolating BMC. - Yakir Vizel; Arie Gurfinkel; Sharad Malik (CAV (1), 2015)

Completeness bounds and sequentialization for model checking of interacting firmware and hardware. - Sunha Ahn; Sharad Malik; Aarti Gupta (CODES+ISSS, 2015)

Hardware Trojan detection for gate-level ICs using signal correlation based clustering. - Burçin Çakir; Sharad Malik (DATE, 2015)

Optimizing dynamic trace signal selection using machine learning and linear programming. - Charlie Shucheng Zhu; Sharad Malik (DATE, 2015)

Detecting Hardware Trojans: A Tale of Two Techniques. - Sharad Malik (FMCAD, 2015)

Template-based Synthesis of Instruction-Level Abstractions for SoC Verification. - Pramod Subramanyan; Yakir Vizel; Sayak Ray; Sharad Malik (FMCAD, 2015)

Evaluating the security of logic encryption algorithms. - Pramod Subramanyan; Sayak Ray; Sharad Malik (HOST, 2015)

Error-Tolerant Processors: Formal Specification and Verification. - Ameneh Golnari; Yakir Vizel; Sharad Malik (ICCAD, 2015)

Boolean Satisfiability Solvers and Their Applications in Model Checking. - Yakir Vizel; Georg Weissenbacher; Sharad Malik (Proc. IEEE, 2015)

Constrained Sampling and Counting: Universal Hashing Meets SAT Solving. - Kuldeep S. Meel; Moshe Y. Vardi; Supratik Chakraborty; Daniel J. Fremont; Sanjit A. Seshia; Dror Fried; Alexander Ivrii; Sharad Malik (AAAI Workshop: Beyond NP, 2016)

Invited - Specification and modeling for systems-on-chip security verification. - Sharad Malik; Pramod Subramanyan (DAC, 2016)

Verifying information flow properties of firmware using symbolic execution. - Pramod Subramanyan; Sharad Malik; Hareesh Khattri; Abhranil Maiti; Jason M. Fung (DATE, 2016)

On computing minimal independent support and its applications to sampling and counting. - Alexander Ivrii; Sharad Malik; Kuldeep S. Meel; Moshe Y. Vardi (Constraints An Int. J., 2016)

Model checking unbounded concurrent lists. - Divjyot Sethi; Muralidhar Talupur; Sharad Malik (Int. J. Softw. Tools Technol. Transf., 2016)

Evaluating matrix representations for error-tolerant computing. - Pareesa Ameneh Golnari; Sharad Malik (DATE, 2017)

Malware detection using machine learning based analysis of virtual memory access patterns. - Zhixing Xu; Sayak Ray; Pramod Subramanyan; Sharad Malik (DATE, 2017)

Solving linear arithmetic with SAT-based model checking. - Yakir Vizel; Alexander Nadel; Sharad Malik (FMCAD, 2017)

Trace-based Analysis of Memory Corruption Malware Attacks. - Zhixing Xu; Aarti Gupta; Sharad Malik (Haifa Verification Conference, 2017)

Solving Constraints over Bit-Vectors with SAT-based Model Checking. - Yakir Vizel; Alexander Nadel; Sharad Malik (SMT, 2017)

IC3 - Flipping the E in ICE. - Yakir Vizel; Arie Gurfinkel; Sharon Shoham; Sharad Malik (VMCAI, 2017)

PPU: A Control Error-Tolerant Processor for Streaming Applications with Formal Guarantees. - Pareesa Ameneh Golnari; Yavuz Yetim; Margaret Martonosi; Yakir Vizel; Sharad Malik (ACM J. Emerg. Technol. Comput. Syst., 2017)

Lazy Self-composition for Security Verification. - Weikun Yang; Yakir Vizel; Pramod Subramanyan; Aarti Gupta; Sharad Malik (CAV (2), 2018)

Formal security verification of concurrent firmware in SoCs using instruction-level abstraction for hardware. - Bo-Yuan Huang 001; Sayak Ray; Aarti Gupta; Jason M. Fung; Sharad Malik (DAC, 2018)

ILA-MCM: Integrating Memory Consistency Models with Instruction-Level Abstractions for Heterogeneous System-on-Chip Verification. - Hongce Zhang; Caroline Trippel; Yatin A. Manerkar; Aarti Gupta; Margaret Martonosi; Sharad Malik (FMCAD, 2018)

Vulnerability-tolerant secure architectures. - Todd M. Austin; Valeria Bertacco; Baris Kasikci; Sharad Malik; Mohit Tiwari (ICCAD, 2018)

A formal instruction-level GPU model for scalable verification. - Yue Xing 001; Bo-Yuan Huang 001; Aarti Gupta; Sharad Malik (ICCAD, 2018)

Template-Based Parameterized Synthesis of Uniform Instruction-Level Abstractions for SoC Verification. - Pramod Subramanyan; Bo-Yuan Huang 001; Yakir Vizel; Aarti Gupta; Sharad Malik (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Reverse Engineering Digital ICs through Geometric Embedding of Circuit Graphs. - Burçin Çakir; Sharad Malik (ACM Trans. Design Autom. Electr. Syst., 2018)

Propositional SAT Solving. - João Marques-Silva 001; Sharad Malik (Handbook of Model Checking, 2018)

Sparse Matrix to Matrix Multiplication: A Representation and Architecture for Acceleration. - Sharad Malik; Pareesa Ameneh Golnari (ASAP, 2019)

Morpheus: A Vulnerability-Tolerant Secure Architecture Based on Ensembles of Moving Target Defenses with Churn. - Mark Gallagher 003; Lauren Biernacki; Shibo Chen 001; Zelalem Birhanu Aweke; Salessawi Ferede Yitbarek; Misiker Tadesse Aga; Austin Harris 001; Zhixing Xu; Baris Kasikci; Valeria Bertacco; Sharad Malik; Mohit Tiwari; et al. (ASPLOS, 2019)

SpFlow: Memory-Driven Data Flow Optimization for Sparse Matrix-Matrix Multiplication. - Qi Nie; Sharad Malik (ISCAS, 2019)

ILAng: A Modeling and Verification Platform for SoCs Using Instruction-Level Abstractions. - Bo-Yuan Huang 001; Hongce Zhang; Aarti Gupta; Sharad Malik (TACAS (1), 2019)

Sparse Matrix to Matrix Multiplication: A Representation and Architecture for Acceleration (long version). - Pareesa Ameneh Golnari; Sharad Malik (CoRR, 2019)

Revealing Cluster Hierarchy in Gate-level ICs Using Block Diagrams and Cluster Estimates of Circuit Embeddings. - Burçin Çakir; Sharad Malik (ACM Trans. Design Autom. Electr. Syst., 2019)

Instruction-Level Abstraction (ILA): A Uniform Specification for System-on-Chip (SoC) Verification. - Bo-Yuan Huang 001; Hongce Zhang; Pramod Subramanyan; Yakir Vizel; Aarti Gupta; Sharad Malik (ACM Trans. Design Autom. Electr. Syst., 2019)

Synthesizing Environment Invariants for Modular Hardware Verification. - Hongce Zhang; Weikun Yang; Grigory Fedyukovich; Aarti Gupta; Sharad Malik (VMCAI, 2020)

MemFlow: Memory-Driven Data Scheduling With Datapath Co-Design in Accelerators for Large-Scale Inference Applications. - Qi Nie; Sharad Malik (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Leveraging Processor Modeling and Verification for General Hardware Modules. - Yue Xing 001; Huaixi Lu; Aarti Gupta; Sharad Malik (DATE, 2021)

Generating Architecture-Level Abstractions from RTL Designs for Processors and Accelerators Part I: Determining Architectural State Variables. - Yu Zeng; Bo-Yuan Huang 001; Hongce Zhang; Aarti Gupta; Sharad Malik (ICCAD, 2021)

Syntax-Guided Synthesis for Lemma Generation in Hardware Model Checking. - Hongce Zhang; Aarti Gupta; Sharad Malik (VMCAI, 2021)

Software-driven Security Attacks: From Vulnerability Sources to Durable Hardware Defenses. - Lauren Biernacki; Mark Gallagher 003; Zhixing Xu; Misiker Tadesse Aga; Austin Harris 001; Shijia Wei; Mohit Tiwari; Baris Kasikci; Sharad Malik; Todd M. Austin (ACM J. Emerg. Technol. Comput. Syst., 2021)

Conflict-Driven Clause Learning SAT Solvers. - João Marques-Silva 001; Inês Lynce; Sharad Malik (Handbook of Satisfiability, 2021)

Generalizing Tandem Simulation: Connecting High-level and RTL Simulation Models. - Yue Xing 001; Aarti Gupta; Sharad Malik (ASP-DAC, 2022)

Automatic Generation of Architecture-Level Models from RTL Designs for Processors and Accelerators. - Yu Zeng; Aarti Gupta; Sharad Malik (DATE, 2022)

Usage-Based RTL Subsetting for Hardware Accelerators. - Qinhan Tan; Aarti Gupta; Sharad Malik (ICCAD, 2022)

Compositional Verification Using a Formal Component and Interface Specification. - Yue Xing 001; Huaixi Lu; Aarti Gupta; Sharad Malik (ICCAD, 2022)

Specialized Accelerators and Compiler Flows: Replacing Accelerator APIs with a Formal Software/Hardware Interface. - Bo-Yuan Huang 001; Steven Lyubomirsky; Yi Li; Mike He; Thierry Tambe; Gus Henry Smith; Akash Gaonkar; Vishal Canumalla; Gu-Yeon Wei; Aarti Gupta; Zachary Tatlock; Sharad Malik (CoRR, 2022)

Security Verification of Low-Trust Architectures. - Qinhan Tan; Yonathan Fisseha; Shibo Chen 001; Lauren Biernacki; Jean-Baptiste Jeannin; Sharad Malik; Todd M. Austin (CCS, 2023)

INVITED: Generalizing the ISA to the ILA: A Software/Hardware Interface for Accelerator-rich Platforms. - Bo-Yuan Huang 001; Hongce Zhang; Aarti Gupta; Sharad Malik (DAC, 2023)

Combined Scheduling, Memory Allocation and Tensor Replacement for Minimizing Off-Chip Data Accesses of DNN Accelerators. - Yi Li; Aarti Gupta; Sharad Malik (CoRR, 2023)

CNNFlow: Memory-driven Data Flow Optimization for Convolutional Neural Networks. - Qi Nie; Sharad Malik (ACM Trans. Design Autom. Electr. Syst., 2023)

SoC Protocol Implementation Verification Using Instruction-Level Abstraction Specifications. - Huaixi Lu; Yue Xing 001; Aarti Gupta; Sharad Malik (ACM Trans. Design Autom. Electr. Syst., 2023)

Exact Scheduling to Minimize Off-Chip Data Movement for Deep Learning Accelerators. - Yi Li; Aarti Gupta; Sharad Malik (ASPDAC, 2024)

Automatic Verification and Identification of Partial Retention Register Sets for Low-Power Designs. - Yu-An Shih; Sharad Malik (ICCAD, 2024)

Automatic Generation of Cycle-Accurate Timing Models from RTL for Hardware Accelerators. - Yu Zeng; Aarti Gupta; Sharad Malik (ICCAD, 2024)

Application-level Validation of Accelerator Designs Using a Formal Software/Hardware Interface. - Bo-Yuan Huang 001; Steven Lyubomirsky; Yi Li; Mike He; Gus Henry Smith; Thierry Tambe; Akash Gaonkar; Vishal Canumalla; Andrew Cheung; Gu-Yeon Wei; Aarti Gupta; Zachary Tatlock; et al. (ACM Trans. Design Autom. Electr. Syst., 2024)

Formal Verification for Secure Processors: A Guide for Computer Architects. - Mengjia Yan 001; Thomas Bourgeat; Sharad Malik (Computer, 2024)

RTL Verification for Secure Speculation Using Contract Shadow Logic. - Qinhan Tan; Yuheng Yang; Thomas Bourgeat; Sharad Malik; Mengjia Yan 001 (ASPLOS (1), 2025)

FLAG: Formal and LLM-assisted SVA Generation for Formal Specifications of On-Chip Communication Protocols. - Yu-An Shih; Annie Lin; Aarti Gupta; Sharad Malik (CoRR, 2025)

Hierarchical Formal Verification of Hardware. - Huaixi Lu; Yue Xing 001; Aarti Gupta; Sharad Malik (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)