A Novel Binding Algorithm to Reduce Critical Path Delay During High Level Synthesis. - Sharad Sinha; Udit Dhawan; Siew Kei Lam; Thambipillai Srikanthan (ISVLSI, 2011)

Dataflow graph partitioning for high level synthesis. - Sharad Sinha; Thambipillai Srikanthan (FPL, 2012)

A Bit-Level Block Cipher Diffusion Analysis Test - BLDAT. - Dipanjan Bhowmik; Avijit Datta; Sharad Sinha (FICTA (1), 2014)

IP-Enabled C/C++ Based High Level Synthesis: A Step towards Better Designer Productivity and Design Performance. - Sharad Sinha; Thambipillai Srikanthan (Int. J. Reconfigurable Comput., 2014)

Architecture and Application-Aware Management of Complexity of Mapping Multiplication to FPGA DSP Blocks in High Level Synthesis. - Sharad Sinha; Thambipillai Srikanthan (Int. J. Reconfigurable Comput., 2014)

Extended Compatibility Path Based Hardware binding: an Adaptive Algorithm for High Level synthesis of Area-Time Efficient Designs. - Sharad Sinha; Udit Dhawan; Thambipillai Srikanthan (J. Circuits Syst. Comput., 2014)

Dataflow Graph Partitioning for Area-Efficient High-Level Synthesis with Systems Perspective. - Sharad Sinha; Thambipillai Srikanthan (ACM Trans. Design Autom. Electr. Syst., 2014)

Intelligent high level synthesis for customization on reconfigurable platforms - Sharad Sinha (2014)

Static hardware task placement on multi-context FPGA using hybrid genetic algorithm. - Hao Liang 003; Sharad Sinha; Rakesh Warrier; Wei Zhang 012 (FPL, 2015)

Hierarchical library based power estimator for versatile FPGAs. - Hao Liang 003; Wei Zhang 012; Sharad Sinha; Yi-Chung Chen; Hai Li 001 (FPL, 2015)

Analytical Delay Model for CPU-FPGA Data Paths in Programmable System-on-Chip FPGA. - Mohammad Tahghighi; Sharad Sinha; Wei Zhang 012 (ARC, 2016)

Area Efficient Hardware Architecture for Implicitly-Defined Complex Events Processing. - Mohammad Tahghighi; Wei Zhang 012; Sharad Sinha (ISVLSI, 2016)

Low-Power FPGA Design Using Memoization-Based Approximate Computing. - Sharad Sinha; Wei Zhang 012 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

PAAS: A system level simulator for heterogeneous computing architectures. - Tingyuan Liang; Liang Feng 001; Sharad Sinha; Wei Zhang 012 (FPL, 2017)

Decision tree based hardware power monitoring for run time dynamic power management in FPGA. - Zhe Lin 007; Wei Zhang 012; Sharad Sinha (FPL, 2017)

A hybrid approach to cache management in heterogeneous CPU-FPGA platforms. - Liang Feng 001; Sharad Sinha; Wei Zhang 012; Yun Liang 001 (ICCAD, 2017)

COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications. - Jieru Zhao; Liang Feng 001; Sharad Sinha; Wei Zhang 012; Yun Liang 001; Bingsheng He (ICCAD, 2017)

HeteroSim: A Heterogeneous CPU-FPGA Simulator. - Liang Feng 001; Hao Liang 003; Sharad Sinha; Wei Zhang 012 (IEEE Comput. Archit. Lett., 2017)

CAMAS: Static and Dynamic Hybrid Cache Management for CPU-FPGA Platforms. - Liang Feng 001; Sharad Sinha; Wei Zhang 012; Yun Liang 001 (FCCM, 2018)

A Collaborative Framework for FPGA-based CNN Design Modeling and Optimization. - Jiandong Mu; Wei Zhang 012; Hao Liang 003; Sharad Sinha (FPL, 2018)

Parallelizing Hardware Tasks on Multicontext FPGA With Efficient Placement and Scheduling Algorithms. - Hao Liang 003; Sharad Sinha; Wei Zhang 012 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Hi-DMM: High-Performance Dynamic Memory Management in High-Level Synthesis. - Tingyuan Liang; Jieru Zhao; Liang Feng 001; Sharad Sinha; Wei Zhang 012 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors. - Zhe Lin 007; Sharad Sinha; Hao Liang 003; Liang Feng 001; Wei Zhang 012 (IEEE Trans. Multi Scale Comput. Syst., 2018)

LAMA: Link-Aware Hybrid Management for Memory Accesses in Emerging CPU-FPGA Platforms. - Liang Feng 001; Jieru Zhao; Tingyuan Liang; Sharad Sinha; Wei Zhang 012 (DAC, 2019)

Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis. - Jieru Zhao; Tingyuan Liang; Sharad Sinha; Wei Zhang 012 (DATE, 2019)

Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGA. - Zhe Lin 007; Sharad Sinha; Wei Zhang 012 (FCCM, 2019)

A Hybrid Data-Consistent Framework for Link-Aware AccessManagement in Emerging CPU-FPGA Platforms. - Liang Feng 001; Jieru Zhao; Tingyuan Liang; Sharad Sinha; Wei Zhang 012 (FPGA, 2019)

Hi-ClockFlow: Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis. - Tingyuan Liang; Jieru Zhao; Liang Feng 001; Sharad Sinha; Wei Zhang 012 (ICCAD, 2019)

Smart Nation: Offline Public Transport Made Easy. - Ang Poh Keong; K. G. Smitha; Sharad Sinha (ICITE, 2019)

Smart Nation: Indoor Navigation for the Visually Impaired. - Lim Boon Leng; Smitha K. G.; Sharad Sinha (ICITE, 2019)

Optimization of Convolutional Neural Networks on Resource Constrained Devices. - Arish S; Sharad Sinha; Smitha K. G. (ISVLSI, 2019)

Artificial intelligence for all using R programming language. - Sharad Sinha; Clint P. George (AI Matters, 2019)

An Ensemble Learning Approach for In-Situ Monitoring of FPGA Dynamic Power. - Zhe Lin 007; Sharad Sinha; Wei Zhang 012 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis. - Zhe Lin 007; Jieru Zhao; Sharad Sinha; Wei Zhang 012 (ASP-DAC, 2020)

iGPU Leak: An Information Leakage Vulnerability on Intel Integrated GPU. - Wenjian He; Wei Zhang 012; Sharad Sinha; Sanjeev Das (ASP-DAC, 2020)

FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications. - Jieru Zhao; Tingyuan Liang; Liang Feng 001; Wenchao Ding 001; Sharad Sinha; Wei Zhang 012; Shaojie Shen (FPL, 2020)

DASH: Design Automation for Synthesis and Hardware Generation for CNN. - Arish Sateesan; Sharad Sinha; Smitha K. G. (FPT, 2020)

Performance Modeling and Directives Optimization for High-Level Synthesis on FPGA. - Jieru Zhao; Liang Feng 001; Sharad Sinha; Wei Zhang 012; Yun Liang 001; Bingsheng He (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Optimizing OpenCL-Based CNN Design on FPGA with Comprehensive Design Space Exploration and Collaborative Performance Modeling. - Jiandong Mu; Wei Zhang 012; Hao Liang 003; Sharad Sinha (ACM Trans. Reconfigurable Technol. Syst., 2020)

Exploiting Weight Statistics for Compressed Neural Network Implementation on Hardware. - Prachi Kashikar; Sharad Sinha; Ajeet Kumar Verma (AICAS, 2021)

Load-Step: A Precise TrustZone Execution Control Framework for Exploring New Side-channel Attacks Like Flush+Evict. - Zili Kou; Wenjian He; Sharad Sinha; Wei Zhang 012 (DAC, 2021)

AMF-Placer: High-Performance Analytical Mixed-size Placer for FPGA. - Tingyuan Liang; Gengjie Chen; Jieru Zhao; Sharad Sinha; Wei Zhang 012 (ICCAD, 2021)

Compressing CNNs by Exponent Sharing in Weights using IEEE Single Precision Format. - Prachi Kashikar; Sharad Sinha (ISQED, 2021)

Detection of Cache Side Channel Attacks Using Thread Level Monitoring of Hardware Performance Counters. - Pavitra Prakash Bhade; Sharad Sinha (MCSoC, 2021)

Variable Bit-Precision Vector Extension for RISC-V Based Processors. - Risikesh RK; Sharad Sinha; Nanditha P. Rao (MCSoC, 2021)

A Survey of Algorithmic and Hardware Optimization Techniques for Vision Convolutional Neural Networks on FPGAs. - Arish Sateesan; Sharad Sinha; Smitha K. G.; A. P. Vinod 001 (Neural Process. Lett., 2021)

Hard-ODT: Hardware-Friendly Online Decision Tree Learning Algorithm and System. - Zhe Lin 007; Sharad Sinha; Wei Zhang 012 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Machine Learning Based Webcasting Analytics for Indian Elections - Reflections on Deployment. - Aditi Saxena; Sharad Sinha (CVIP (2), 2022)

Attack Directories on ARM big.LITTLE Processors. - Zili Kou; Sharad Sinha; Wenjian He; Wei Zhang 012 (ICCAD, 2022)

Workings of science: Is engineering applied science? - Sharad Sinha (Ubiquity, 2022)

YOLORe-IDNet: An Efficient Multi-camera System for Person-Tracking. - Vipin Gautam; Shitala Prasad; Sharad Sinha (CVIP (1), 2023)

Joint-YODNet: A Light-Weight Object Detector for UAVs to Achieve Above 100fps. - Vipin Gautam; Shitala Prasad; Sharad Sinha (CVIP (2), 2023)

Cache Side-channel Attacks and Defenses of the Sliding Window Algorithm in TEEs. - Zili Kou; Sharad Sinha; Wenjian He; Wei Zhang 012 (DATE, 2023)

Tensor-Product-Based Accelerator for Area-efficient and Scalable Number Theoretic Transform. - Yuying Zhang; Sathi Sarveswara Reddy; Zili Kou; Sharad Sinha; Wei Zhang 012 (FCCM, 2023)

FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs. - Linfeng Du; Tingyuan Liang; Sharad Sinha; Zhiyao Xie; Wei Zhang 012 (FPGA, 2023)

DiffLo: A Graph-based Method for Functional Discrepancy Localization in High-level Synthesis. - Liangji Chen; Tingyuan Liang; Wei Zhang 012; Sharad Sinha (ICFPT, 2023)

Message from Workshop Chairs. - Sheikh K. Ghafoor; Sushil K. Prasad; Ashish Kuvelkar; Sharad Sinha; Satish Puri (HiPCW, 2023)

AaP-ReID: Improved Attention-Aware Person Re-identification. - Vipin Gautam; Shitala Prasad; Sharad Sinha (CoRR, 2023)

Design and Analysis of RSA and Paillier Homomorphic Cryptosystems Using PSO-Based Evolutionary Computation. - Sathi Sarveswara Reddy; Sharad Sinha; Wei Zhang 012 (IEEE Trans. Computers, 2023)

HL-Pow: Learning-Assisted Pre-RTL Power Modeling and Optimization for FPGA HLS. - Zhe Lin 007; Tingyuan Liang; Jieru Zhao; Sharad Sinha; Wei Zhang 012 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Lossless Neural Network Model Compression Through Exponent Sharing. - Prachi Kashikar; Olivier Sentieys; Sharad Sinha (IEEE Trans. Very Large Scale Integr. Syst., 2023)

GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network. - Chunyou Su; Linfeng Du; Tingyuan Liang; Zhe Lin 007; Maolin Wang 002; Sharad Sinha; Wei Zhang 012 (FPGA, 2024)

ConvMap: Boosting Convolution Throughput on FPGAs with Efficient Resource Mapping. - Shubhayu Das; Nanditha P. Rao; Sharad Sinha (IPDPS (Workshops), 2024)

VATML: Towards On Device Ventricular Arrhythmia Detection Using TinyML. - Vipin Gautam; Sharad Sinha; Shitala Prasad (iSES, 2024)

Mender-FPGA: An Open Source Framework for FPGA Remote Update for ML Applications. - Nikita Rathor; Sharad Sinha (iSES, 2024)

Advancing microbial diagnostics: a universal phylogeny guided computational algorithm to find unique sequences for precise microorganism detection. - Gulshan Kumar Sharma; Rakesh Sharma 003; Kavita Joshi; Sameer Qureshi; Shubhita Mathur; Sharad Sinha; Samit Chatterjee; Vandana Nunia (Briefings Bioinform., 2024)

Shielding against online harm: A survey on text analysis to prevent cyberbullying. - Akanksha Mishra; Sharad Sinha; Clint Pazhayidam George (Eng. Appl. Artif. Intell., 2024)

Lightweight Hardware-Based Cache Side-Channel Attack Detection for Edge Devices (Edge-CaSCADe). - Pavitra Prakash Bhade; Joseph Paturel; Olivier Sentieys; Sharad Sinha (ACM Trans. Embed. Comput. Syst., 2024)

Unveiling the Advantages of Full Coherency Architecture for FPSoC Systems. - Enlai Li; Sharad Sinha; Wei Zhang 012 (IEEE Trans. Very Large Scale Integr. Syst., 2024)

AMF-Placer 2.0: Open-Source Timing-Driven Analytical Mixed-Size Placer for Large-Scale Heterogeneous FPGA. - Tingyuan Liang; Gengjie Chen; Jieru Zhao; Sharad Sinha; Wei Zhang 012 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

FADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAs. - Linfeng Du; Tingyuan Liang; Xiaofeng Zhou; Jinming Ge; Shangkun Li; Sharad Sinha; Jieru Zhao; Zhiyao Xie; Wei Zhang 012 (ACM Trans. Reconfigurable Technol. Syst., 2024)

Combining Weight Approximation, Sharing and Retraining for Neural Network Model Compression. - Prachi Kashikar; Olivier Sentieys; Sharad Sinha (ACM Trans. Embed. Comput. Syst., 2024)

UNIT: A Highly Unified and Memory-Efficient FPGA-Based Accelerator for Torus FHE. - Yuying Zhang; Sharad Sinha; Jiang Xu; Wei Zhang (DATE, 2025)

TAPCA: An Interface-Aware Cache Management Framework for Task Partitioning on CPU-FPGA SoC Platforms. - Enlai Li; Zhe Lin 007; Sharad Sinha; Wei Zhang 012 (FPGA, 2025)