Pre-synthesis Optimization for Asynchronous Circuits Using Compiler Techniques. - Sharareh Zamanzadeh; Mehrdad Najibi; Hossein Pedram (CSICC, 2008)

Reimbursing the Handshake Overhead of Asynchronous Circuits using Compiler Pre-Synthesis Optimizations. - Sharareh Zamanzadeh; Mohammad Mirza-Aghatabar; Mehrdad Najibi; Hossein Pedram; Abolghasem Sadeghi (DSD, 2008)

Automatic netlist scrambling methodology in ASIC design flow to hinder the reverse engineering. - Sharareh Zamanzadeh; Ali Jahanian 001 (VLSI-SoC, 2013)

Design, analysis, and implementation of partial product reduction phase by using wide m: 3 (4 ≤ m ≤ 10) compressors. - Shima Mehrabi; Reza Faghih Mirzaee; Sharareh Zamanzadeh; Keivan Navi; Omid Hashemipour (Int. J. High Perform. Syst. Archit., 2013)

Security improvement of FPGA configuration file against the reverse engineering attack. - Sharareh Zamanzadeh; Shahram Shahabi; Ali Jahanian 001 (ISCISC, 2016)

Security Path: An Emerging Design Methodology to Protect the FPGA IPs Against Passive/Active Design Tampering. - Sharareh Zamanzadeh; Ali Jahanian 001 (J. Electron. Test., 2016)

Self authentication path insertion in FPGA-based design flow for tamper-resistant purpose. - Sharareh Zamanzadeh; Ali Jahanian 001 (ISC Int. J. Inf. Secur., 2016)

ASIC design protection against reverse engineering during the fabrication process using automatic netlist obfuscation design flow. - Sharareh Zamanzadeh; Ali Jahanian 001 (ISC Int. J. Inf. Secur., 2016)

Higher security of ASIC fabrication process against reverse engineering attack using automatic netlist encryption methodology. - Sharareh Zamanzadeh; Ali Jahanian 001 (Microprocess. Microsystems, 2016)

Scalable security path methodology: A cost-security trade-off to protect FPGA IPs against active and passive tampers. - Sharareh Zamanzadeh; Ali Jahanian 001 (AsianHOST, 2017)