A 200-MHz 64-bit Dual-Issue CMOS Microprocessor. - Daniel W. Dobberpuhl; Richard T. Witek; Randy L. Allmon; Robert Anglin; David Bertucci; Sharon M. Britton; Linda Chao; Robert A. Conrad; Daniel E. Dever; Bruce Gieseke; Soha Hassoun; Gregory W. Hoeppner; et al. (Digit. Tech. J., 1992)

A 200-MHz 64-b dual-issue CMOS microprocessor. - Daniel W. Dobberpuhl; Richard T. Witek; Randy L. Allmon; Robert Anglin; David Bertucci; Sharon M. Britton; Linda Chao; Robert A. Conrad; Daniel E. Dever; Bruce Gieseke; Soha Hassoun; Gregory W. Hoeppner; et al. (IEEE J. Solid State Circuits, 1992)

Circuit Implementation of a 300-MHz 64-bit Second-generation CMOS Alpha CPU - William J. Bowhill; Shane L. Bell; Bradley J. Benschneider; Andrew J. Black; Sharon M. Britton; Ruben W. Castelino; Dale R. Donchin; John H. Edmondson; Harry R. Fair III; Paul E. Gronowski; Anil K. Jain 003; Patricia L. Kroesen; et al. (Digit. Tech. J., 1995)

A 300-MHz 64-b quad-issue CMOS RISC microprocessor. - Bradley J. Benschneider; Andrew J. Black; William J. Bowhill; Sharon M. Britton; Daniel E. Dever; Dale R. Donchin; Robert J. Dupcak; Richard M. Fromm; Mary K. Gowan; Paul E. Gronowski; Michael Kantrowitz; Marc E. Lamere; et al. (IEEE J. Solid State Circuits, 1995)