Design of Area Optimised, Energy Efficient Quaternary Circuits Using CNTFETs. - Poojan Patel; Nikita Doddapaneni; Sharvani Gadgil; Chetan Vudadha (iSES, 2019)

A Novel Low Power Ternary Multiplier Design using CNFETs. - Harita Sirugudi; Sharvani Gadgil; Chetan Vudadha (VLSID, 2020)

Design of CNTFET-based Ternary Logic circuits using Low power Encoder. - Siddharth T; Sharvani Gadgil; Chetan Vudadha (iSES, 2022)

Power efficient designs of CNTFET-based ternary SRAM. - Sharvani Gadgil; Goli Naga Sandesh; Chetan Vudadha (Microelectron. J., 2023)

Design of a Ternary Logic Processor Using CNTFET Technology. - Sharvani Gadgil; Goli Naga Sandesh; Chetan Vudadha (Circuits Syst. Signal Process., 2024)