Improved Implementation of CRL and SCRL Gates for Ultra Low Power. - Amit Agarkhed; Sharvil Patil; Anu Gupta (ARTCom, 2009)

A Novel Dynamic Current Boosting Technique for Enhancement of Settling Time and Elimination of Slewing of CMOS Amplifiers. - Ashutosh Mehra 001; Anu Gupta; Sharvil Patil; Abhishek Mehra; Subhendu Kumar Sahoo (ARTCom, 2009)

Continuous-time hybrid computation with programmable nonlinearities. - Ning Guo; Yipeng Huang 001; Tao Mai; Sharvil Patil; Chi Cao; Mingoo Seok; Simha Sethumadhavan; Yannis P. Tsividis (ESSCIRC, 2015)

A 3-10fJ/conv-step 0.0032mm2 error-shaping alias-free asynchronous ADC. - Sharvil Patil; Alin Ratiu; Dominique Morche; Yannis P. Tsividis (VLSIC, 2015)

Derivative Level-Crossing Sampling. - Pablo Martínez-Nuevo; Sharvil Patil; Yannis P. Tsividis (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Digital processing of signals produced by voltage-controlled-oscillator-based continuous-time ADCs. - Sharvil Patil; Yannis P. Tsividis (ISCAS, 2016)

Energy-Efficient Hybrid Analog/Digital Approximate Computation in Continuous Time. - Ning Guo; Yipeng Huang 001; Tao Mai; Sharvil Patil; Chi Cao; Mingoo Seok; Simha Sethumadhavan; Yannis P. Tsividis (IEEE J. Solid State Circuits, 2016)

A 3-10 fJ/conv-step Error-Shaping Alias-Free Continuous-Time ADC. - Sharvil Patil; Alin Ratiu; Dominique Morche; Yannis P. Tsividis (IEEE J. Solid State Circuits, 2016)

A 9-GS/s 1.125-GHz BW Oversampling Continuous-Time Pipeline ADC Achieving -164-dBFS/Hz NSD. - Hajime Shibata; Victor Kozlov; Zexi Ji; Asha Ganesan; Haiyang Zhu; Donald Paterson; Jialin Zhao 001; Sharvil Patil; Shanthi Pavan (IEEE J. Solid State Circuits, 2017)

Corrections to "Energy-Efficient Hybrid Analog/Digital Approximate Computation in Continuous Time". - Ning Guo; Yipeng Huang 001; Tao Mai; Sharvil Patil; Chi Cao; Mingoo Seok; Simha Sethumadhavan; Yannis P. Tsividis (IEEE J. Solid State Circuits, 2018)

Signal Encoding and Processing in Continuous Time Using a Cascade of Digital Delays. - Sharvil Patil; Suhas Gundu Rao; Yu Chen 013; Yannis P. Tsividis (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

16.6 An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter. - Hajime Shibata; Gerry Taylor; Bob Schell; Victor Kozlov; Sharvil Patil; Donald Paterson; Asha Ganesan; Yunzhi Dong; Wenhua Yang 002; Yue Yin; Zhao Li; Prawal Shrestha; et al. (ISSCC, 2020)

A Design Methodology for Achieving Near Nyquist Continuous Time Pipelined ADCs. - Mohammed Wagih Ismail; Hajime Shibata; Zhao Li; Sharvil Patil; Tony Chan Carusone (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 1-MHz-Bandwidth Continuous-Time Delta-Sigma ADC Achieving >90dB SFDR and >80dB Antialiasing Using Reference-Switched Resistive Feedback DACs. - Sharvil Patil; Raviteja Theertham; Hajime Shibata; Victor Kozlov; Asha Ganesan; Efram Burlingame; Zhao Li; Rama Thakar; Qianqian Zhang; Yue Yin; Aathreya S. Bhat (CICC, 2023)

22.2 A 700MHZ-BW -164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving 3 using Digital Cancellation of DAC Errors. - Sharvil Patil; Asha Ganesan; Hajime Shibata; Victor Kozlov; Gerry Taylor; Qingnan Yu; Zhao Li; Zeynep Lulec; Konstantinos Vasilakopoulos; Prawal Shrestha; Donald Paterson; Raviteja Theertham; et al. (ISSCC, 2024)

A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC With Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET. - Rishabh Mittal; Hajime Shibata; Sharvil Patil; Erik Krommenhoek; Prawal Shrestha; Gabriele Manganaro; Anantha P. Chandrakasan; Hae-Seung Lee (IEEE J. Solid State Circuits, 2024)

A -90-dBFS-IM3, -164-dBFS/Hz-NSD, 700-MHz-Bandwidth Continuous-Time Pipelined ADC With Digital Cancellation of DAC Errors. - Sharvil Patil; Asha Ganesan; Hajime Shibata; Victor Kozlov; Gerry Taylor; Prawal Shrestha; Zhao Li; Sevil Zeynep Lulec; Konstantinos Vasilakopoulos; Raviteja Theertham; Donald Paterson; Qingnan Yu; et al. (IEEE J. Solid State Circuits, 2024)