Coordinate rotation and vector cross product based hardware accelerator for nD FastICA. - Swati Bhardwaj 001; Shashank Raghuraman; Amit Acharyya (ECCTD, 2017)

Low complexity hardware accelerator for nD FastICA based on coordinate rotation. - Swati Bhardwaj 001; Shashank Raghuraman; Amit Acharyya (SiPS, 2017)

Coordinate Rotation-Based Low Complexity K-Means Clustering Architecture. - Bhagyaraja Adapa; Dwaipayan Biswas; Swati Bhardwaj 001; Shashank Raghuraman; Amit Acharyya; Koushik Maharatna (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Vector Cross Product and Coordinate Rotation Based nD Hybrid FastICA. - Swati Bhardwaj 001; Shashank Raghuraman; Bhagyaraja Adapa; Amit Acharyya (J. Low Power Electron., 2018)

Simplex FastICA: An Accelerated and Low Complex Architecture Design Methodology for $n$ D FastICA. - Swati Bhardwaj 001; Shashank Raghuraman; Amit Acharyya (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Impact of System-on-Chip Integration of AEAD Ciphers. - Shashank Raghuraman; Leyla Nazhandali (IACR Cryptol. ePrint Arch., 2020)

Low-Complex and Low-Power n-dimensional Gram-Schmidt Orthogonalization Architecture Design Methodology. - Swati Bhardwaj 001; Shashank Raghuraman; Jayesh B. Yerrapragada; Agathya Jagirdar; Koushik Maharatna; Amit Acharyya (Circuits Syst. Signal Process., 2022)