Algorithms for a switch module routing problem. - Shashidhar Thakur; D. F. Wong 001; S. Muthukrishnan 001 (EURO-DAC, 1994)

A new global routing algorithm for FPGAs. - Yao-Wen Chang; Shashidhar Thakur; Kai Zhu 001; D. F. Wong 001 (ICCAD, 1994)

On Designing ULM-based FPGA Logic Modules. - Shashidhar Thakur; D. F. Wong 001 (FPGA, 1995)

An Optimal Layer Assignment Algorithm for Minimizing Crosstalk for Three Layer VHV Channel Routing. - Shashidhar Thakur; Kai-Yuan Chao; D. F. Wong 001 (ISCAS, 1995)

Delay Minimal Decomposition of Multiplexers in Technology Mapping. - Shashidhar Thakur; D. F. Wong 001; Shankar Krishnamoorthy (DAC, 1996)

Universal Logic Modules for Series-Parallel Functions. - Shashidhar Thakur; D. F. Wong 001 (FPGA, 1996)

Simultaneous area and delay minimum K-LUT mapping for K-exact networks. - Shashidhar Thakur; D. F. Wong 001 (Integr., 1996)

Series-parallel functions and FPGA logic module design. - Shashidhar Thakur; D. F. Wong 001 (ACM Trans. Design Autom. Electr. Syst., 1996)

Algorithms for an FPGA switch module routing problem with application to global routing. - Shashidhar Thakur; Yao-Wen Chang; Martin D. F. Wong; S. Muthukrishnan 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Minimum Crosstalk Vertical Layer Assignment for Three-Layer VHV Channel Routing. - Shashidhar Thakur; Kai-Yuan Chao; D. F. Wong 001 (VLSI Design, 1998)

Estimating routing congestion using probabilistic analysis. - Jinan Lou; Shashidhar Thakur; Shankar Krishnamoorthy; Henry S. Sheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Knowledge in Search. - Shashidhar Thakur (NTCIR, 2013)