Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor. - Saurabh Dighe; Sriram R. Vangal; Paolo A. Aseron; Shasi Kumar; Tiju Jacob; Keith A. Bowman; Jason Howard; James W. Tschanz; Vasantha Erraguntla; Nitin Borkar; Vivek De; Shekhar Borkar (ISSCC, 2010)

Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor. - Saurabh Dighe; Sriram R. Vangal; Paolo A. Aseron; Shasi Kumar; Tiju Jacob; Keith A. Bowman; Jason Howard; James W. Tschanz; Vasantha Erraguntla; Nitin Borkar; Vivek K. De; Shekhar Borkar (IEEE J. Solid State Circuits, 2011)

A 2 Tb/s 6 , ˟, 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS. - Praveen Salihundam; Shailendra Jain; Tiju Jacob; Shasi Kumar; Vasantha Erraguntla; Yatin Vasant Hoskote; Sriram R. Vangal; Gregory Ruhl; Nitin Borkar (IEEE J. Solid State Circuits, 2011)

An IA-32 processor with a wide voltage operating range in 32nm CMOS. - Gregory Ruhl; Saurabh Dighe; Shailendra Jain; Surhud Khare; Satish Yada; V. Ambili; Praveen Salihundam; Shiva Ramani; Sriram Muthukumar; M. Srinivasan; Arun Kumar; Shasi Kumar; et al. (Hot Chips Symposium, 2012)

A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS. - Shailendra Jain; Surhud Khare; Satish Yada; V. Ambili; Praveen Salihundam; Shiva Ramani; Sriram Muthukumar; M. Srinivasan; Arun Kumar; Shasi Kumar; Rajaraman Ramanarayanan; Vasantha Erraguntla; et al. (ISSCC, 2012)

A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip. - Praveen Salihundam; Mohammed Asadullah Khan; Shailendra Jain; Yatin Vasant Hoskote; Satish Yada; Shasi Kumar; Vasantha Erraguntla; Sriram R. Vangal; Nitin Borkar (VLSI Design, 2012)