Nearly Ideal Subthreshold Swing and Delay Reduction of Stacked Nanosheets Using Ultrathin Bodies. - Chung-En Tsai; Chun-Yi Cheng; Bo-Wei Huang; Hsin-Cheng Lin; Tao Chou; Chien-Te Tu; Yi-Chun Liu; Sun-Rong Jan; Yu-Rui Chen; Wan-Hsuan Hsieh; Kung-Ying Chiu; Shee-Jier Chueh; et al. (VLSI Technology and Circuits, 2022)

First Stacked Nanosheet FeFET Featuring Memory Window of 1.8V at Record Low Write Voltage of 2V and Endurance >1E11 Cycles. - Yu-Rui Chen; Yi-Chun Liu; Zefu Zhao; Wan-Hsuan Hsieh; Jia-Yang Lee; Chien-Te Tu; Bo-Wei Huang; Jer-Fu Wang; Shee-Jier Chueh; Yifan Xing; Guan-Hua Chen; Hung-Chun Chou; et al. (VLSI Technology and Circuits, 2023)

Extremely High-κ Hf0.2Zr0.8O2 Gate Stacks Integrated into Ge0.95Si0.05 Nanowire and Nanosheet nFETs Featuring Respective Record Ion per Footprint of 9200μA/μm and Record Ion per Stack of 360μA at VOV=VDS=0.5V. - Yi-Chun Liu; Yu-Rui Chen; Yun-Wen Chen; Hsin-Cheng Lin; Wan-Hsuan Hsieh; Chien-Te Tu; Bo-Wei Huang; Wei-Jen Chen; Chun-Yi Cheng; Shee-Jier Chueh; Chee Wee Liu (VLSI Technology and Circuits, 2023)