Towards Optimizing Refresh Energy in embedded-DRAM Caches using Private Blocks. - Sheel Sindhu Manohar; Sukarn Agarwal; Hemangee K. Kapoor (ACM Great Lakes Symposium on VLSI, 2019)

Refresh optimised embedded-dram caches based on zero data detection. - Sheel Sindhu Manohar; Hemangee K. Kapoor (SAC, 2019)

Dynamic reconfiguration of embedded-DRAM caches employing zero data detection based refresh optimisation. - Sheel Sindhu Manohar; Hemangee K. Kapoor (J. Syst. Archit., 2019)

CORIDOR: Using COherence and TempoRal LocalIty to Mitigate Read Disurbance ErrOR in STT-RAM Caches. - Sheel Sindhu Manohar; Sparsh Mittal; Hemangee K. Kapoor (ACM Trans. Embed. Comput. Syst., 2022)

CAPMIG: Coherence-Aware Block Placement and Migration in Multiretention STT-RAM Caches. - Sheel Sindhu Manohar; Hemangee K. Kapoor (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)