Warp: an integrated solution of high-speed parallel computing. - Shekhar Borkar; Robert Cohn; George W. Cox; Sha Gleason; Thomas R. Gross (SC, 1988)

Supporting Systolic and Memory Communciation in iWarp. - Shekhar Borkar; Robert Cohn; George W. Cox; Thomas R. Gross; H. T. Kung 001; Monica Lam 001; Margie Levine; Brian Moore 004; Wire Moore; Craig Peterson; Jim Susman; Jim Sutton; et al. (ISCA, 1990)

A 900 Mb/s bidirectional signaling scheme. - Randy Mooney; Charles Dike; Shekhar Borkar (IEEE J. Solid State Circuits, 1995)

Technology and design challenges for low power and high performance. - Vivek De; Shekhar Borkar (ISLPED, 1999)

Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's. - Ali Keshavarzi; Siva G. Narendra; Shekhar Borkar; Charles F. Hawkins; Kaushik Roy 001; Vivek De (ISLPED, 1999)

Accurate on-chip interconnect evaluation: a time-domain technique. - Krishnamurthy Soumyanath; Shekhar Borkar; Chunyan Zhou; Bradley A. Bloechel (IEEE J. Solid State Circuits, 1999)

Design challenges of technology scaling. - Shekhar Borkar (IEEE Micro, 1999)

Low power and high performance design challenges in future technologies. - Vivek De; Shekhar Borkar (ACM Great Lakes Symposium on VLSI, 2000)

Low power design challenges for the decade (invited talk). - Shekhar Borkar (ASP-DAC, 2001)

Panel: Is Nanometer Design Under Control? - Andrew B. Kahng; Bing J. Sheu; Nancy Nettleton; John M. Cohn; Shekhar Borkar; Louis Scheffer; Ed Cheng; Sang Wang (DAC, 2001)

Leakage control and tolerance challenges for sub-0.1µm microprocessor circuits. - Ram Krishnamurthy 001; Mark A. Anders 001; Krishnamurthy Soumyanath; Shekhar Borkar (ACM Great Lakes Symposium on VLSI, 2001)

A low-leakage dynamic multi-ported register file in 0.13mm CMOS. - Atila Alvandpour; Ram Krishnamurthy 001; Krishnamurthy Soumyanath; Shekhar Borkar (ISLPED, 2001)

Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs. - Ali Keshavarzi; Sean Ma; Siva G. Narendra; Brad Bloechel; K. Mistry; Tahir Ghani; Shekhar Borkar; Vivek De (ISLPED, 2001)

Scaling of stack effect and its application for leakage reduction. - Siva G. Narendra; Vivek De; Dimitri A. Antoniadis; Anantha P. Chandrakasan; Shekhar Borkar (ISLPED, 2001)

Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors. - James W. Tschanz; Siva G. Narendra; Zhanping Chen; Shekhar Borkar; Manoj Sachdev; Vivek De (ISLPED, 2001)

A burn-in tolerant dynamic circuit technique. - Atila Alvandpour; Ram Krishnamurthy 001; Shekhar Borkar; A. Rahman; Clair Webb (CICC, 2002)

High-performance and low-power challenges for sub-70 nm microprocessor circuits. - Ram K. Krishnamurthy; Atila Alvandpour; Vivek De; Shekhar Borkar (CICC, 2002)

Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors. - Tanay Karnik; Yibin Ye; James W. Tschanz; Liqiong Wei; Steven M. Burns; Venkatesh Govindarajulu; Vivek De; Shekhar Borkar (DAC, 2002)

Life is CMOS: why chase the life after? - George Sery; Shekhar Borkar; Vivek De (DAC, 2002)

Sub-90nm technologies: challenges and opportunities for CAD. - Tanay Karnik; Shekhar Borkar; Vivek De (ICCAD, 2002)

Full-chip sub-threshold leakage power prediction model for sub-0.18 µm CMOS. - Siva G. Narendra; Vivek De; Shekhar Borkar; Dimitri A. Antoniadis; Anantha P. Chandrakasan (ISLPED, 2002)

A sub-130-nm conditional keeper technique. - Atila Alvandpour; Ram K. Krishnamurthy; Krishnamurthy Soumyanath; Shekhar Y. Borkar (IEEE J. Solid State Circuits, 2002)

A 130-nm 6-GHz 256 × 32 bit leakage-tolerant register file. - Ram K. Krishnamurthy; Atila Alvandpour; Ganesh Balamurugan; Naresh R. Shanbhag; Krishnamurthy Soumyanath; Shekhar Y. Borkar (IEEE J. Solid State Circuits, 2002)

5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS. - Sriram R. Vangal; Mark A. Anders 001; Nitin Borkar; Erik Seligman; Venkatesh Govindarajulu; Vasantha Erraguntla; Howard Wilson; Amaresh Pangal; Venkat Veeramachaneni; James W. Tschanz; Yibin Ye; Dinesh Somasekhar; et al. (IEEE J. Solid State Circuits, 2002)

Guest editorial. - Masakazu Yamashina; Shekhar Y. Borkar (IEEE J. Solid State Circuits, 2002)

Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache. - Fatih Hamzaoglu; Yibin Ye; Ali Keshavarzi; Kevin Zhang 001; Siva G. Narendra; Shekhar Borkar; Mircea R. Stan; Vivek De (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process. - Peter Hazucha; Tanay Kamik; Steven Walstra; Bradley A. Bloechel; James W. Tschanz; Jose Maiz; Krishnamurthy Soumyanath; Greg Dermer; Siva G. Narendra; Vivek De; Shekhar Borkar (CICC, 2003)

Parameter variations and impact on circuits and microarchitecture. - Shekhar Borkar; Tanay Karnik; Siva G. Narendra; James W. Tschanz; Ali Keshavarzi; Vivek De (DAC, 2003)

Nanometer design: place your bets. - Andrew B. Kahng; Shekhar Borkar; John M. Cohn; Antun Domic; Patrick Groeneveld; Louis Scheffer; Jean-Pierre Schoellkopf (DAC, 2003)

Bitline leakage equalization for sub-100nm caches. - Atila Alvandpour; Dinesh Somasekhar; Ram Krishnamurthy 001; Vivek De; Shekhar Borkar; Christer Svensson (ESSCIRC, 2003)

Low voltage sensing techniques and secondary design issues for sub-90nm caches. - Manoj Sinha; Steven Hsu; Atila Alvandpour; Wayne P. Burleson; Ram Krishnamurthy 001; Shekhar Borkar (ESSCIRC, 2003)

Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies. - Bhaskar Chatterjee; Manoj Sachdev; Steven Hsu; Ram Krishnamurthy 001; Shekhar Borkar (ISLPED, 2003)

Exponential Challenges, Exponential Rewards - The future of Moore's Law. - Shekhar Borkar (VLSI-SOC, 2003)

A transition-encoded dynamic bus technique for high-performance interconnects. - Mark A. Anders 001; Nivruti Rai; Ram K. Krishnamurthy; Shekhar Borkar (IEEE J. Solid State Circuits, 2003)

Guest Editorial. - Shekhar Borkar; Yoshinobu Nakagome (IEEE J. Solid State Circuits, 2003)

A 4.5-GHz 130-nm 32-KB L0 cache with a leakage-tolerant self reverse-bias bitline scheme. - Steven Hsu; Atila Alvandpour; Sanu Mathew; Shih-Lien Lu; Ram K. Krishnamurthy; Shekhar Borkar (IEEE J. Solid State Circuits, 2003)

A 4-GHz 130-nm address generation unit with 32-bit sparse-tree adder core. - Sanu Mathew; Mark A. Anders 001; Ram K. Krishnamurthy; Shekhar Borkar (IEEE J. Solid State Circuits, 2003)

Forward body bias for microprocessors in 130-nm technology generation and beyond. - Siva G. Narendra; Ali Keshavarzi; Bradley A. Bloechel; Shekhar Borkar; Vivek De (IEEE J. Solid State Circuits, 2003)

Dynamic sleep transistor and body bias for active leakage power control of microprocessors. - James W. Tschanz; Siva G. Narendra; Yibin Ye; Bradley A. Bloechel; Shekhar Borkar; Vivek De (IEEE J. Solid State Circuits, 2003)

Getting Gigascale Chips: Challenges and Opportunities in Continuing Moore's Law. - Shekhar Borkar (ACM Queue, 2003)

Design and reliability challenges in nanometer technologies. - Shekhar Borkar; Tanay Karnik; Vivek De (DAC, 2004)

Is statistical timing statistically significant? - Richard Goldman; Kurt Keutzer; Clive Bittlestone; Ahsan Bootehsaz; Shekhar Y. Borkar; E. Chen; Louis Scheffer; Chandramouli Visweswariah (DAC, 2004)

A low-swing single-ended L1 cache bus technique for sub-90nm technologies. - Peter Caputa; Mark A. Anders 001; Christer Svensson; Ram K. Krishnamurthy; Shekhar Borkar (ESSCIRC, 2004)

Microarchitecture and Design Challenges for Gigascale Integration. - Shekhar Borkar (MICRO, 2004)

Measurements and analysis of SER-tolerant latch in a 90-nm dual-VT CMOS process. - Peter Hazucha; Tanay Karnik; Steven Walstra; Bradley A. Bloechel; James W. Tschanz; Jose Maiz; Krishnamurthy Soumyanath; Gregory E. Dermer; Siva G. Narendra; Vivek De; Shekhar Borkar (IEEE J. Solid State Circuits, 2004)

Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-μm CMOS. - Siva G. Narendra; Vivek De; Shekhar Borkar; Dimitri A. Antoniadis; Anantha P. Chandrakasan (IEEE J. Solid State Circuits, 2004)

Self Calibrating Circuit Design for Variation Tolerant VLSI Systems. - Chris H. Kim; Steven Hsu; Ram Krishnamurthy 001; Shekhar Borkar; Kaushik Roy 001 (IOLTS, 2005)

An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS. - Steven Hsu; Amit Agarwal 001; Kaushik Roy 001; Ram Krishnamurthy 001; Shekhar Borkar (ISLPED, 2005)

VLSI Design Challenges for Gigascale Integration. - Shekhar Borkar (VLSI Design, 2005)

Area-efficient linear regulator with ultra-fast load regulation. - Peter Hazucha; Tanay Karnik; Bradley A. Bloechel; Colleen Parsons; David Finan; Shekhar Borkar (IEEE J. Solid State Circuits, 2005)

A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package. - Peter Hazucha; Gerhard Schrom; Jaehong Hahn; Bradley A. Bloechel; Paul Hack; Gregory E. Dermer; Siva G. Narendra; Donald S. Gardner; Tanay Karnik; Vivek De; Shekhar Borkar (IEEE J. Solid State Circuits, 2005)

A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems. - Joseph T. Kennedy; Randy Mooney; Robert Ellis; James E. Jaussi; Shekhar Borkar; Jung-Hwan Choi; Jae-Kwan Kim 003; Chan-Kyong Kim; Woo-Seop Kim; Chang-Hyun Kim; Soo-In Cho; Steffen Loeffler; et al. (IEEE J. Solid State Circuits, 2005)

A 4-GHz 300-mW 64-bit integer execution ALU with dual supply voltages in 90-nm CMOS. - Sanu K. Mathew; Mark A. Anders 001; Brad Bloechel; Trang Nguyen; Ram K. Krishnamurthy; Shekhar Borkar (IEEE J. Solid State Circuits, 2005)

Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation. - Shekhar Borkar (IEEE Micro, 2005)

Electronics beyond nano-scale CMOS. - Shekhar Borkar (DAC, 2006)

Tomorrow's analog: just dead or just different? - Shekhar Borkar; Robert W. Brodersen; Jue-Hsien Chern; Eric Naviasky; D. Saias; Charles G. Sodini (DAC, 2006)

An 8.8GHz 198mW 16x64b 1R/1W variationtolerant register file in 65nm CMOS. - Steven K. Hsu; Amit Agarwal 001; Mark A. Anders 001; Sanu Mathew; Ram Krishnamurthy 001; Shekhar Borkar (ISSCC, 2006)

Introduction to panel discussion Probabilistic & statistical design - the wave of the future. - Shekhar Borkar (VLSI-SoC, 2006)

Probabilistic amp; Statistical Design - the Wave of the Future. - Shekhar Borkar (VLSI-SoC (Selected Papers), 2006)

Tackling variability and reliability challenges. - Shekhar Borkar (IEEE Des. Test Comput., 2006)

A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS. - Steven K. Hsu; Sanu K. Mathew; Mark A. Anders 001; Bart R. Zeydel; Vojin G. Oklobdzija; Ram K. Krishnamurthy; Shekhar Y. Borkar (IEEE J. Solid State Circuits, 2006)

A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits. - Chris H. Kim; Kaushik Roy 001; Steven Hsu; Ram Krishnamurthy 001; Shekhar Borkar (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Thousand Core ChipsA Technology Perspective. - Shekhar Borkar (DAC, 2007)

Microprocessors in the era of terascale integration. - Shekhar Borkar; Norman P. Jouppi; Per Stenström (DATE, 2007)

Future of on-chip interconnection architectures. - Shekhar Borkar; William J. Dally (ISLPED, 2007)

A 1.9Gb/s 358mW 16-to-256 State Reconfigurable Viterbi Accelerator in 90nm CMOS. - Mark A. Anders 001; Sanu Mathew; Steven Hsu; Ram Krishnamurthy 001; Shekhar Borkar (ISSCC, 2007)

A 5-GHz Mesh Interconnect for a Teraflops Processor. - Yatin Hoskote; Sriram R. Vangal; Arvind P. Singh; Nitin Borkar; Shekhar Borkar (IEEE Micro, 2007)

Custom is from Venus and synthesis from Mars. - Ruchir Puri; William H. Joyner; Shekhar Borkar; Ty Garibay; Jonathan Lotz; Robert K. Montoye (DAC, 2008)

A 2.9Tb/s 8W 64-core circuit-switched network-on-chip in 45nm CMOS. - Mark A. Anders 001; Himanshu Kaul; Martin Hansson; Ram Krishnamurthy 001; Shekhar Borkar (ESSCIRC, 2008)

A 320mV 56μW 411GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65nm CMOS. - Himanshu Kaul; Mark A. Anders 001; Sanu Mathew; Steven Hsu; Amit Agarwal 001; Ram Krishnamurthy 001; Shekhar Borkar (ISSCC, 2008)

2GHz 2Mb 2T Gain-Cell Memory Macro with 128GB/s Bandwidth in a 65nm Logic Process. - Dinesh Somasekhar; Yibin Ye; Paolo A. Aseron; Shih-Lien Lu; Muhammad M. Khellah; Jason Howard; Gregory Ruhl; Tanay Karnik; Shekhar Y. Borkar; Vivek De; Ali Keshavarzi (ISSCC, 2008)

Thousand-Core Chips [Roundtable]. - David Yeh; Li-Shiuan Peh; Shekhar Borkar; John A. Darringer; Anant Agarwal; Wen-mei W. Hwu (IEEE Des. Test Comput., 2008)

A 1.9 Gb/s 358 mW 16-256 State Reconfigurable Viterbi Accelerator in 90 nm CMOS. - Mark A. Anders 001; Sanu K. Mathew; Steven Hsu; Ram K. Krishnamurthy; Shekhar Borkar (IEEE J. Solid State Circuits, 2008)

An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS. - Sriram R. Vangal; Jason Howard; Gregory Ruhl; Saurabh Dighe; Howard Wilson; James W. Tschanz; David Finan; Arvind P. Singh; Tiju Jacob; Shailendra Jain; Vasantha Erraguntla; Clark Roberts; et al. (IEEE J. Solid State Circuits, 2008)

Design perspectives on 22nm CMOS and beyond. - Shekhar Borkar (DAC, 2009)

Circuit techniques for dynamic variation tolerance. - Keith A. Bowman; James W. Tschanz; Chris Wilkerson; Shih-Lien Lu; Tanay Karnik; Vivek De; Shekhar Y. Borkar (DAC, 2009)

A 300mV 494GOPS/W reconfigurable dual-supply 4-Way SIMD vector processing accelerator in 45nm CMOS. - Himanshu Kaul; Mark A. Anders 001; Sanu Mathew; Steven Hsu; Amit Agarwal 001; Ram Krishnamurthy 001; Shekhar Borkar (ISSCC, 2009)

A 320 mV 56 μW 411 GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65 nm CMOS. - Himanshu Kaul; Mark A. Anders 001; Sanu K. Mathew; Steven Hsu; Amit Agarwal 001; Ram K. Krishnamurthy; Shekhar Borkar (IEEE J. Solid State Circuits, 2009)

2 GHz 2 Mb 2T Gain Cell Memory Macro With 128 GBytes/sec Bandwidth in a 65 nm Logic Process Technology. - Dinesh Somasekhar; Yibin Ye; Paolo A. Aseron; Shih-Lien Lu; Muhammad M. Khellah; Jason Howard; Gregory Ruhl; Tanay Karnik; Shekhar Borkar; Vivek K. De; Ali Keshavarzi (IEEE J. Solid State Circuits, 2009)

A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOS. - Amit Agarwal 001; Sanu Mathew; Steven Hsu; Mark A. Anders 001; Himanshu Kaul; Farhana Sheikh; Rajaraman Ramanarayanan; Suresh Srinivasan; Ram Krishnamurthy 001; Shekhar Borkar (ISSCC, 2010)

A 4.1Tb/s bisection-bandwidth 560Gb/s/W streaming circuit-switched 8×8 mesh network-on-chip in 45nm CMOS. - Mark A. Anders 001; Himanshu Kaul; Steven Hsu; Amit Agarwal 001; Sanu Mathew; Farhana Sheikh; Ram Krishnamurthy 001; Shekhar Borkar (ISSCC, 2010)

The semiconductor industry in 2025. - Azeez Bhavnagarwala; Shekhar Borkar; Takayasu Sakurai; Siva G. Narendra (ISSCC, 2010)

Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor. - Saurabh Dighe; Sriram R. Vangal; Paolo A. Aseron; Shasi Kumar; Tiju Jacob; Keith A. Bowman; Jason Howard; James W. Tschanz; Vasantha Erraguntla; Nitin Borkar; Vivek De; Shekhar Borkar (ISSCC, 2010)

A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS. - Jason Howard; Saurabh Dighe; Yatin Vasant Hoskote; Sriram R. Vangal; David Finan; Gregory Ruhl; David Jenkins; Howard Wilson; Nitin Borkar; Gerhard Schrom; Fabric Pailet; Shailendra Jain; et al. (ISSCC, 2010)

Future of interconnect fabric: a contrarian view. - Shekhar Y. Borkar (SLIP, 2010)

Want to be a bug buster? - Shekhar Y. Borkar (Commun. ACM, 2010)

A 300 mV 494GOPS/W Reconfigurable Dual-Supply 4-Way SIMD Vector Processing Accelerator in 45 nm CMOS. - Himanshu Kaul; Mark A. Anders 001; Sanu Mathew; Steven Hsu; Amit Agarwal 001; Ram Krishnamurthy 001; Shekhar Borkar (IEEE J. Solid State Circuits, 2010)

Hybrid Circuit/Packet Switched Network for Energy Efficient on-Chip Interconnections. - Mark A. Anders 001; Himanshu Kaul; Ram K. Krishnamurthy; Shekhar Y. Borkar (Low Power Networks-on-Chip, 2011)

3D integration for energy efficient system design. - Shekhar Borkar (DAC, 2011)

Integrated inductors with magnetic materials for on-chip power conversion. - Donald S. Gardner; Gerhard Schrom; Fabrice Paillet; Tanay Karnik; Shekhar Borkar (Hot Chips Symposium, 2011)

3DICs for tera-scale computing: a case study. - Tanay Karnik; Dinesh Somasekhar; Shekhar Borkar (ISPD, 2011)

The future of microprocessors. - Shekhar Borkar; Andrew A. Chien (Commun. ACM, 2011)

Microprocessor system applications and challenges for through-silicon-via-based three-dimensional integration. - Tanay Karnik; Dinesh Somasekhar; Shekhar Borkar (IET Comput. Digit. Tech., 2011)

Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor. - Saurabh Dighe; Sriram R. Vangal; Paolo A. Aseron; Shasi Kumar; Tiju Jacob; Keith A. Bowman; Jason Howard; James W. Tschanz; Vasantha Erraguntla; Nitin Borkar; Vivek K. De; Shekhar Borkar (IEEE J. Solid State Circuits, 2011)

A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling. - Jason Howard; Saurabh Dighe; Sriram R. Vangal; Gregory Ruhl; Nitin Borkar; Shailendra Jain; Vasantha Erraguntla; Michael Konow; Michael Riepen; Matthias Gries; Guido Droege; Tor Lund-Larsen; et al. (IEEE J. Solid State Circuits, 2011)

Near-threshold voltage (NTV) design: opportunities and challenges. - Himanshu Kaul; Mark A. Anders 001; Steven Hsu; Amit Agarwal 001; Ram Krishnamurthy 001; Shekhar Borkar (DAC, 2012)

On the Role of Co-design in High Performance Computing. - Richard F. Barrett; Shekhar Borkar; Sudip S. Dosanjh; Simon D. Hammond; Michael A. Heroux; Xiaobo Sharon Hu; Justin Luitjens; Steven G. Parker; John Shalf; Li Tang 007 (High Performance Computing Workshop (2), 2012)

A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS. - Shailendra Jain; Surhud Khare; Satish Yada; V. Ambili; Praveen Salihundam; Shiva Ramani; Sriram Muthukumar; M. Srinivasan; Arun Kumar; Shasi Kumar; Rajaraman Ramanarayanan; Vasantha Erraguntla; et al. (ISSCC, 2012)

A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS. - Himanshu Kaul; Mark A. Anders 001; Sanu Mathew; Steven Hsu; Amit Agarwal 001; Farhana Sheikh; Ram Krishnamurthy 001; Shekhar Borkar (ISSCC, 2012)

Session 18 overview: Innovative circuits in emerging technologies: Technology directions subcommittee. - Masaitsu Nakajima; Shekhar Borkar (ISSCC, 2012)

A 2.05GVertices/s 151mW lighting accelerator for 3D graphics vertex and pixel shading in 32nm CMOS. - Farhana Sheikh; Sanu Mathew; Mark A. Anders 001; Himanshu Kaul; Steven Hsu; Amit Agarwal 001; Ram Krishnamurthy 001; Shekhar Borkar (ISSCC, 2012)

A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS. - Steven Hsu; Amit Agarwal 001; Mark A. Anders 001; Himanshu Kaul; Sanu Mathew; Farhana Sheikh; Ram Krishnamurthy 001; Shekhar Borkar (VLSIC, 2012)

Power management and delivery for high-performance microprocessors. - Tanay Karnik; Mondira (Mandy) Deb Pant; Shekhar Borkar (DAC, 2013)

Runnemede: An architecture for Ubiquitous High-Performance Computing. - Nicholas P. Carter; Aditya Agrawal; Shekhar Borkar; Romain Cledat; Howard David; Dave Dunning; Joshua B. Fryman; Ivan Ganev; Roger A. Golliver; Rob C. Knauerhase; Richard Lethin; Benoît Meister; et al. (HPCA, 2013)

Exascale Computing - A Fact or a Fiction? - Shekhar Borkar (IPDPS, 2013)

EP3: Empowering the killer SoC applications of 2020. - Shekhar Borkar; Uming Ko; Ali Keshavarzi; Eugenio Cantatore (ISSCC, 2013)

Centip3De demonstrates more than Moore...: technical perspective. - Shekhar Borkar (Commun. ACM, 2013)

A 2.05 GVertices/s 151 mW Lighting Accelerator for 3D Graphics Vertex and Pixel Shading in 32 nm CMOS. - Farhana Sheikh; Sanu Mathew; Mark A. Anders 001; Himanshu Kaul; Steven Hsu; Amit Agarwal 001; Ram K. Krishnamurthy; Shekhar Borkar (IEEE J. Solid State Circuits, 2013)

Resiliency for many-core system on a chip. - Tanay Karnik; James W. Tschanz; Nitin Borkar; Jason Howard; Sriram R. Vangal; Vivek De; Shekhar Borkar (ASP-DAC, 2014)

Characterization of radiation-induced SRAM and logic soft errors from 0.33V to 1.0V in 65nm CMOS. - Robert Pawlowski; Joseph Crop; Minki Cho; James W. Tschanz; Vivek De; Thomas Fairbanks; Heather Quinn; Shekhar Borkar; Patrick Yin Chiang (CICC, 2014)

16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS. - Gregory K. Chen; Mark A. Anders 001; Himanshu Kaul; Sudhir Satpathy; Sanu K. Mathew; Steven K. Hsu; Amit Agarwal 001; Ram K. Krishnamurthy; Shekhar Borkar; Vivek De (ISSCC, 2014)

Circuits evening panel discussion 1: Is university circuit design research and education keeping up with industry needs? - P. Yue; Bing J. Sheu; A. Matsuzawa; K. Asada; L. Loh; Kofi A. A. Makinwa; Shekhar Borkar; Vladimir Stojanovic (VLSIC, 2015)

A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS. - Gregory K. Chen; Mark A. Anders 001; Himanshu Kaul; Sudhir Satpathy; Sanu K. Mathew; Steven Hsu; Amit Agarwal 001; Ram Krishnamurthy 001; Vivek De; Shekhar Borkar (IEEE J. Solid State Circuits, 2015)

Extreme Energy Efficiency by Near Threshold Voltage Operation. - Shekhar Borkar (Near Threshold Computing, 2016)

Traleika Glacier: A hardware-software co-designed approach to exascale computing. - Vincent Cavé; Romain Cledat; Paul Griffin; Ankit More; Bala Seshasayee; Shekhar Borkar; Sanjay Chatterjee; Dave Dunning; Joshua B. Fryman (Parallel Comput., 2017)

Security Closure of Physical Layouts ICCAD Special Session Paper. - Johann Knechtel; Jayanth Gopinath; Jitendra Bhandari; Mohammed Ashraf; Hussam Amrouch; Shekhar Borkar; Sung Kyu Lim; Ozgur Sinanoglu; Ramesh Karri (ICCAD, 2021)