The CORDIC Householder algorithm. - Shen-Fu Hsiao; Jean-Marc Delosme (IEEE Symposium on Computer Arithmetic, 1991)

Parallel processing of complex data using quaternion and pseudo-quaternion CORDIC algorithms. - Shen-Fu Hsiao; Jean-Marc Delosme (ASAP, 1994)

Adaptive Jacobi method for parallel singular value decompositions. - Shen-Fu Hsiao (ICASSP, 1995)

Householder CORDIC Algorithms. - Shen-Fu Hsiao; Jean-Marc Delosme (IEEE Trans. Computers, 1995)

Parallel singular value decomposition of complex matrices using multidimensional CORDIC algorithms. - Shen-Fu Hsiao; Jean-Marc Delosme (IEEE Trans. Signal Process., 1996)

New unified VLSI architectures for computing DFT and other transforms. - Shen-Fu Hsiao; Chung-Yi Yen (ICASSP, 1997)

Design, Implementation and Analysis of a New Redundant CORDIC Processor with Constant Scaling Factor and Regular Structure. - Shen-Fu Hsiao; Jen-Yin Chen (J. VLSI Signal Process., 1998)

A high-throughput, low power architecture and its VLSI implementation for DFT/IDFT computation. - Shen-Fu Hsiao; Wei-Ren Shiue (ICASSP, 1999)

New hardware-efficient algorithm and architecture for the computation of 2-D DCT on a linear systolic array. - Shen-Fu Hsiao; Wei-Ren Shiue (ICASSP, 1999)

Design and performance verification of ALUs for 64-bit 8-issue superscaler microprocessors using 0.25 um CMOS technology. - Chua-Chin Wang; Sheng-Hua Chen; Shen-Fu Hsiao; Chuan-Lin Wu (ICECS, 1999)

A high-speed constant-factor redundant CORDIC processor without extra correcting or scaling iterations. - Shen-Fu Hsiao (ISCAS (1), 1999)

A cost-efficient and fully-pipelinable architecture for DCT/IDCT. - Shen-Fu Hsiao; Wei-Ren Shiue; Jian-Ming Tseng (IEEE Trans. Consumer Electron., 1999)

Low-cost unified architectures for the computation of discrete trigonometric transforms. - Shen-Fu Hsiao; Wei-Ren Shiue (ICASSP, 2000)

VLSI design of an efficient embedded zerotree wavelet coder with function of digital watermarking. - Shen-Fu Hsiao; Yor-Chin Tai; Kai-Hsiang Chang (IEEE Trans. Consumer Electron., 2000)

Redundant Constant-Factor Implementation of Multi-Dimensional CORDIC and Its Application to Complex SVD. - Shen-Fu Hsiao; Chun-Yi Lau; Jean-Marc Delosme (J. VLSI Signal Process., 2000)

A new hardware-efficient algorithm and architecture for computation of 2-D DCTs on a linear array. - Shen-Fu Hsiao; Wei-Ren Shiue (IEEE Trans. Circuits Syst. Video Technol., 2001)

Parallel, Pipelined and Folded Architectures for Computation of 1-D and 2-D DCT in Image and Video Codec. - Shen-Fu Hsiao; Jian-Ming Tseng (J. VLSI Signal Process., 2001)

Partition methodology for the final adder in a tree-structure parallel multiplier generator. - Tso-Bing Juang; Jeng-Hsiun Jan; Ming-Yu Tsai; Shen-Fu Hsiao (APCCAS (1), 2002)

High-performance Multiplexer-based Logic Synthesis Using Pass-transistor Logic. - Shen-Fu Hsiao; Jia-Siang Yeh; Da-Yen Chen (VLSI Design, 2002)

Design and implementation of a video-oriented network-interface-card system. - Ming-Chih Chen; Shen-Fu Hsiao; Cheng-Hsien Yang (ASP-DAC, 2003)

A memory-efficient and high-speed sine/cosine generator based on parallel CORDIC rotations. - Shen-Fu Hsiao; Yu Hen Hu; Tso-Bing Juang (IEEE Signal Process. Lett., 2004)

Para-CORDIC: parallel CORDIC rotation algorithm. - Tso-Bing Juang; Shen-Fu Hsiao; Ming-Yu Tsai (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

An efficient pass-transistor-logic synthesizer using multiplexers and inverters only. - Shen-Fu Hsiao; Ming-Yu Tsai; Ming-Chih Chen; Chia-Sheng Wen (ISCAS (3), 2005)

A Cell-Driven Multiplier Generator with Delay Optimization of Partial Products Compression and an Efficient Partition Technique for the Final Addition. - Tso-Bing Juang; Shen-Fu Hsiao; Ming-Yu Tsai; Jenq-Shiun Jan (IEICE Trans. Inf. Syst., 2005)

Efficient VLSI Implementations of Fast Multiplierless Approximated DCT Using Parameterized Hardware Modules for Silicon Intellectual Property Design. - Shen-Fu Hsiao; Yu Hen Hu; Tso-Bing Juang; Cheng-Han Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

Low-error carry-free fixed-width multipliers with low-cost compensation circuits. - Tso-Bing Juang; Shen-Fu Hsiao (IEEE Trans. Circuits Syst. II Express Briefs, 2005)

An Automatic Cache Generator Based on Content-Addressable Memory. - Shen-Fu Hsiao; Sze-Yun Lin; Tze-Chong Cheng; Ming-Yu Tsai (APCCAS, 2006)

Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits. - Shen-Fu Hsiao; Ming-Yu Tsai; Chia-Sheng Wen (APCCAS, 2006)

Novel Memory Organization and Circuit Designs for Efficient Data Access in Applications of 3D Graphics and Multimedia Coding. - Shen-Fu Hsiao; Yo-Chi Chen; Ming-Yu Tsai; Tze-Chong Cheng (MTDT, 2006)

Memory-free low-cost designs of advanced encryption standard using common subexpression elimination for subfunctions in transformations. - Shen-Fu Hsiao; Ming-Chih Chen; Chia-Shin Tu (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

Efficient pre-clipping and clipping algorithms for 3D graphics geometry computation. - Shen-Fu Hsiao; Yuan-Nan Chang; Tze-Ching Tien; Kun-Chih Chen (APCCAS, 2008)

Efficient designs of flaoting-point CORDIC rotation and vectoring operations. - Shen-Fu Hsiao; Hsin-Mau Lee; Yen-Chun Cheng; Ming-Yu Tsai (APCCAS, 2008)

Area oriented pass-transistor logic synthesis using buffer elimination and layout compaction. - Shen-Fu Hsiao; Ming-Yu Tsai; Chia-Sheng Wen (ISCAS, 2008)

An automatic hardware generator for special arithmetic functions using various ROM-based approximation approaches. - Shen-Fu Hsiao; Ping-Chung Wei; Ching-Pin Lin (ISCAS, 2008)

An 8.69 Mvertices/s 278 Mpixels/s tile-based 3D graphics SoC HW/SW development for consumer electronics. - Liang-Bi Chen; Ruei-Ting Gu; Wei-Sheng Huang; Chien-Chou Wang; Wen-Chi Shiue; Tsung-Yu Ho; Yun-Nan Chang; Shen-Fu Hsiao; Chung-Nan Lee; Ing-Jer Huang (ASP-DAC, 2009)

Low Cost Design of an Advanced Encryption Standard (AES) Processor Using a New Common-Subexpression-Elimination Algorithm. - Ming-Chih Chen; Shen-Fu Hsiao (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Design of table-based function evaluators with reduced memory size Using a bottom-up non-uniform segmentation method. - Shen-Fu Hsiao; Chia-Sheng Wen; Kun-Chih Chen (APCCAS, 2010)

A new non-uniform segmentation and addressing remapping strategy for hardware-oriented function evaluators based on polynomial approximation. - Hou-Jen Ko; Shen-Fu Hsiao; Wen-Liang Huang (ISCAS, 2010)

Low Area/Power Synthesis Using Hybrid Pass Transistor/CMOS Logic Cells in Standard Cell-Based Design Environment. - Shen-Fu Hsiao; Ming-Yu Tsai; Chia-Sheng Wen (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Designs of angle-rotation in digital frequency synthesizer/mixer using multi-stage architectures. - Shen-Fu Hsiao; Cheng-Han Lee; Yen-Chun Cheng; Andrew Lee (ACSCC, 2011)

Design and Application of Faithfully Rounded and Truncated Multipliers With Combined Deletion, Reduction, Truncation, and Rounding. - Hou-Jen Ko; Shen-Fu Hsiao (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

Asynchronous AHB bus interface designs in a multiple-clock-domain graphics system. - Shen-Fu Hsiao; Chi-Guang Lin; Po-Han Wu; Chia-Sheng Wen (APCCAS, 2012)

Low-cost designs of rectangular to polar coordinate converters for digital communication. - Shen-Fu Hsiao; Chia-Sheng Wen; Cheng-Han Lee; Andrew Lee (APCCAS, 2012)

Low latency design of Depth-Image-Based Rendering using hybrid warping and hole-filling. - Shen-Fu Hsiao; Jin-Wen Cheng; Wen-Ling Wang; Guan-Fu Yeh (ISCAS, 2012)

Two-Level Hardware Function Evaluation Based on Correction of Normalized Piecewise Difference Functions. - Shen-Fu Hsiao; Hou-Jen Ko; Chia-Sheng Wen (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Design of a programmable vertex processor in OpenGL ES 2.0 mobile graphics processing units. - Shen-Fu Hsiao; Po-Han Wu; Chia-Sheng Wen; Li-Yao Chen (VLSI-DAT, 2013)

Low-Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple Constant Multiplication/Accumulation. - Shen-Fu Hsiao; Jun-Hong Zhang Jian; Ming-Chih Chen (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

Design of Hardware Function Evaluators Using Low-Overhead Nonuniform Segmentation With Address Remapping. - Shen-Fu Hsiao; Hou-Jen Ko; Yu-Ling Tseng; Wen-Liang Huang; Shin-Hung Lin; Chia-Sheng Wen (IEEE Trans. Very Large Scale Integr. Syst., 2013)

VLSI implementation of belief-propagation-based stereo matching with linear-model message update. - Shen-Fu Hsiao; Jun-Ming Huang; Po-Sheng Wu (APCCAS, 2014)

Compression of Lookup Table for Piecewise Polynomial Function Evaluation. - Shen-Fu Hsiao; Chia-Sheng Wen; Po-Han Wu (DSD, 2014)

Design and Implementation of Multiple-Vehicle Detection and Tracking Systems with Machine Learning. - Shen-Fu Hsiao; Guan-Fu Yeh; Je-Chi Chen (DSD, 2014)

Design of low-leakage multi-port SRAM for register file in graphics processing unit. - Shen-Fu Hsiao; Pu-Cheng Wu (ISCAS, 2014)

VLSI implementations of stereo matching using Dynamic Programming. - Shen-Fu Hsiao; Wen-Ling Wang; Po-Sheng Wu (VLSI-DAT, 2014)

Low-power and high-performance design of OpenGL ES 2.0 graphics processing unit for mobile applications. - Shen-Fu Hsiao; Shang-Yu Li; Kai-Hsiang Tsao (DSP, 2015)

An OpenGL ES 2.0 3D graphics SoC with versatile HW/SW development support. - Hsu-Kang Dow; Ching-Hua Huang; Chun-Hung Lai; Kai-Hsiang Tsao; Sheng-Chih Tseng; Kun-Yi Wu; Ting-Hsuan Wu; Ho-Chun Yang; Da-Jing Zhang-Jian; Yun-Nan Chang; Steve Haga; Shen-Fu Hsiao; et al. (VLSI-DAT, 2015)

Table Size Reduction Methods for Faithfully Rounded Lookup-Table-Based Multiplierless Function Evaluation. - Shen-Fu Hsiao; Po-Han Wu; Chia-Sheng Wen; Pramod Kumar Meher (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Hardware design of histograms of oriented gradients based on local binary pattern and binarization. - Shen-Fu Hsiao; Jun-Mao Chan; Ching-Hui Wang (APCCAS, 2016)

Low-power dual-precision table-based function evaluation supporting dynamic precision changes. - Shen-Fu Hsiao; Kuei-Chun Huang (APCCAS, 2016)

Hardware efficient implementation of histograms of oriented gradients for pedestrian detection. - Shen-Fu Hsiao; Tz-Heng Tz-Heng You (GCCE, 2017)

Hierarchical Multipartite Function Evaluation. - Shen-Fu Hsiao; Chia-Sheng Wen; Yi-Hau Chen; Kuei-Chun Huang (IEEE Trans. Computers, 2017)

Architectural Exploration of Function Computation Based on Cubic Polynomial Interpolation with Application in Deep Neural Networks. - Shen-Fu Hsiao; Yu-Chang Chen; Hsiang-Hao Liang (DSD, 2018)

Design and Implementation of Low-Cost LK Optical Flow Computation for Images of Single and Multiple Levels. - Shen-Fu Hsiao; Chen-Yen Tsai (DSD, 2018)

Design Tradeoff of Internal Memory Size and Memory Access Energy in Deep Neural Network Hardware Accelerators. - Shen-Fu Hsiao; Pei-Hsuen Wu (GCCE, 2018)

Optimization of Lookup Table Size in Table-Bound Design of Function Computation. - Shen-Fu Hsiao; Kun-Chih Chen; Yi-Hau Chen (ISCAS, 2018)

Hardware design of disparity computation for stereo vision using guided image filtering. - Shen-Fu Hsiao; Chih-Hsuan Chang (VLSI-DAT, 2018)

Multi-Precision Table-Addition Designs for Computing Nonlinear Functions in Deep Neural Networks. - Shen-Fu Hsiao; Kuey-Chin Huang; Yu-Hong Chen (APCCAS, 2019)

Low-Complexity Deep Neural Networks for Image Object Classification and Detection. - Shen-Fu Hsiao; Jing-Fu Zhan; Chih-Chien Lin (APCCAS, 2019)

Dual-Precision Acceleration of Convolutional Neural Network Computation with Mixed Input and Output Data Reuse. - Shen-Fu Hsiao; Pei-Hsuan Wu; Jien-Min Chen; Kun-Chih Chen (ISCAS, 2019)

Sparsity-Aware Deep Learning Accelerator Design Supporting CNN and LSTM Operations. - Shen-Fu Hsiao; Hsuan-Jui Chang (ISCAS, 2020)

Hardware Efficient Function Computation Based on Optimized Piecewise Polynomial Approximation. - Shen-Fu Hsiao; Chia-Yang Wong; Yu-Chang Chen (ISCAS, 2020)

Flexible Multi-Precision Accelerator Design for Deep Convolutional Neural Networks Considering Both Data Computation and Communication. - Shen-Fu Hsiao; Yu-Hong Chen (VLSI-DAT, 2020)

Design of a Sparsity-Aware Reconfigurable Deep Learning Accelerator Supporting Various Types of Operations. - Shen-Fu Hsiao; Kun-Chih Chen; Chih-Chien Lin; Hsuan-Jui Chang; Bo-Ching Tsai (IEEE J. Emerg. Sel. Topics Circuits Syst., 2020)

Multi-threaded System Design of A Multi-Precision Deep Learning Accelerator on FPGA with Optimized Memory Usage. - Shen-Fu Hsiao; Jyun-Liang Chen; Yi Hsu; Xiang-Ting Huang (ICCE-TW, 2021)

Efficient Computation of Depthwise Separable Convolution in MoblieNet Deep Neural Network Models. - Shen-Fu Hsiao; Bo-Ching Tsai (ICCE-TW, 2021)

Quantization of Deep Neural Network Models Considering Per-Layer Computation Complexity for Efficient Execution in Multi-Precision Accelerators. - Shen-Fu Hsiao; Yu-Che Yen (ICCE-TW, 2021)

Comparison of Digit-Serial and Bit-Level Designs for Acceleration of Convolutional Neural Network Computation. - Shen-Fu Hsiao; Jian-Ming Chen; Yu-Hong Chen; Hung-Ching Li; Yi Hsu (ISCAS, 2021)

Efficient Quantization and Multi-Precision Design of Arithmetic Components for Deep Learning. - Shen-Fu Hsiao; Yu-Chang Chen; Yu-Che Yen (ISCAS, 2021)

A Power Effective DLA for PBs in Opto-Electrical Neural Network Architecture. - Ralph Gerard B. Sangalang; Shih-Heng Luo; Hsin-Che Wu; Bao-Qi He; Shen-Fu Hsiao; Chua-Chin Wang; Chewnpu Jou; Harry Hsia; Douglas C.-H. Yu (APCCAS, 2022)

Dynamically Swappable Digit-Serial Multi-Precision Deep Neural Network Accelerator with Early Termination. - Shen-Fu Hsiao; Hung-Ching Li; Yu-Che Yen; Po-Chang Li (ISCAS, 2022)

A 40.96-GOPS 196.8-mW Digital Logic Accelerator Used in DNN for Underwater Object Recognition. - Chua-Chin Wang; Ralph Gerard B. Sangalang; Chien-Ping Kuo; Hsin-Che Wu; Yi Hsu; Shen-Fu Hsiao; Chia-Hung Yeh (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Hardware Accelerator for MobileViT Vision Transformer with Reconfigurable Computation. - Shen-Fu Hsiao; Tzu-Hsien Chao; Yen-Che Yuan; Kun-Chih Chen (ISCAS, 2024)

Neural Network Acceleration Using Digit-Plane Computation with Early Termination. - Shen-Fu Hsiao; Hou-Chun Kuo; Yu Kuo; Kun-Chih Chen (ISCAS, 2024)