CMOS four-quadrant multiplier using bias feedback techniques. - Shen-Iuan Liu; Yuh-Shyan Hwang (IEEE J. Solid State Circuits, 1994)

New dynamic flip-flops for high-speed dual-modulus prescaler. - Ching-Yuan Yang; Guang-Kaai Dehng; June-Ming Hsu; Shen-Iuan Liu (IEEE J. Solid State Circuits, 1998)

A cyclic CMOS time-to-digital converter with deep sub-nanosecond resolution. - Poki Chen; Shen-Iuan Liu (CICC, 1999)

Low-power clock-deskew buffer for high-speed digital circuits. - Shen-Iuan Liu; Jiunn-Hwa Lee; Hen-Wai Tsao (IEEE J. Solid State Circuits, 1999)

Clock-deskew buffer using a SAR-controlled delay-locked loop. - Guang-Kaai Dehng; June-Ming Hsu; Ching-Yuan Yang; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2000)

A 900-MHz 1-V CMOS frequency synthesizer. - Guang-Kaai Dehng; Ching-Yuan Yang; June-Ming Hsu; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2000)

A double-sampling pseudo-two-path bandpass ΔΣ modulator. - Shen-Iuan Liu; Chien-Hung Kuo; Ruey-Yuan Tsai; Jingshown Wu (IEEE J. Solid State Circuits, 2000)

Fast-switching frequency synthesizer with a discriminator-aided phase detector. - Ching-Yuan Yang; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2000)

CMOS oversampling Sigma-Delta magnetic to digital converters. - Lee-An Ho; Shr-Lung Chen; Chien-Hung Kuo; Shen-Iuan Liu (ISCAS (1), 2001)

A CMOS 400-Mb/s serial link for AS-memory systems using a PWM scheme. - Wei-Hung Chen; Guang-Kaai Dehang; Jong-Woei Chen; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2001)

A fast-lock mixed-mode DLL using a 2-b SAR algorithm. - Guang-Kaai Dehng; Jyh-Woei Lin; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2001)

CMOS oversampling ΔΣ magnetic-to-digital converters. - Chien-Hung Kuo; Shr-Lung Chen; Lee-An Ho; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2001)

An 8-bit 10 MS/s folding and interpolating ADC using the continuous-time auto-zero technique. - Ming-Huang Liu; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2001)

A one-wire approach for skew-compensating clock distribution based on bidirectional techniques. - Ching-Yuan Yang; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2001)

A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay. - Hsiang-Hui Chang; Jyh-Woei Lin; Shen-Iuan Liu (CICC, 2002)

CMOS 2.4-GHz receiver front end with area-efficient inductors and digitally calibrated 90° delay network. - Chih-Chun Tang; Chia-Hsin Wu; Kun-Hsien Li; Tai-Cheng Lee; Shen-Iuan Liu (ISCAS (3), 2002)

A wide-range delay-locked loop with a fixed latency of one clock cycle. - Hsiang-Hui Chang; Jyh-Woei Lin; Ching-Yuan Yang; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2002)

Miniature 3-D inductors in standard CMOS process. - Chih-Chun Tang; Chia-Hsin Wu; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2002)

A shifted-averaging VCO with precise multiphase outputs and low jitter operation. - Hsiang-Hui Chang; Shang-Ping Chen; Shen-Iuan Liu (ESSCIRC, 2003)

CMOS Tunable 1/x Circuit and Its Applications. - Weihsing Liu; Shen-Iuan Liu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

A spread-spectrum clock generator with triangular modulation. - Hsiang-Hui Chang; I-Hui Hua; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2003)

A fast locking and low jitter delay-locked loop using DHDL. - Hsiang-Hui Chang; Jyh-Woei Lin; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2003)

Analysis of on-chip spiral inductors using the distributed capacitance model. - Chia-Hsin Wu; Chih-Chun Tang; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2003)

A 1V 4.2mW fully integrated 2.5Gb/s CMOS limiting amplifier using folded active inductors. - Chia-Hsin Wu; Jieh-Wei Liao; Shen-Iuan Liu (ISCAS (1), 2004)

A 500-MHz-1.25-GHz fast-locking pulsewidth control loop with presettable duty cycle. - Sung-Rung Han; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2004)

A 1-V 10.7-MHz fourth-order bandpass ΔΣ modulators using two switched op amps. - Chien-Hung Kuo; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2004)

A low voltage-power 13-bit 16 MSPS CMOS pipelined ADC. - Ming-Huang Liu; Kuo-Chan Huang; Wei-Yang Ou; Tsung-Yi Su; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2004)

A 3.125-Gb/s clock and data recovery circuit for the 10-Gbase-LX4 Ethernet. - Rong-Jyi Yang; Shang-Ping Chen; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2004)

Low jitter and multirate clock and data recovery circuit using a MSADLL for chip-to-chip interconnection. - Hsiang-Hui Chang; Rong-Jyi Yang; Shen-Iuan Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

A broadband noise-canceling CMOS LNA for 3.1-10.6-GHz UWB receiver. - Chih-Fan Liao; Shen-Iuan Liu (CICC, 2005)

A tunable bandpass ΔΣ modulator using double sampling. - Chien-Hung Kuo; Chang-Hung Chen; Huang-Shih Lin; Shen-Iuan Liu (ISCAS (4), 2005)

A 15 mW 69 dB 2 Gsamples/s CMOS analog front-end for low-band UWB applications. - Hua-Chin Lee; Chien-Chih Lin; Chia-Hsin Wu; Shen-Iuan Liu; Chorng-Kuang Wang; Hen-Wai Tsao (ISCAS (1), 2005)

A Wide-Range Multiphase Delay-Locked Loop Using Mixed-Mode VCDLs. - Rong-Jyi Yang; Shen-Iuan Liu (IEICE Trans. Electron., 2005)

A Fully Integrated 1.7-3.125 Gbps Clock and Data Recovery Circuit Using a Gated Frequency Detector. - Rong-Jyi Yang; Shen-Iuan Liu (IEICE Trans. Electron., 2005)

A wide-range and fast-locking all-digital cycle-controlled delay-locked loop. - Hsiang-Hui Chang; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2005)

A single-path pulsewidth control loop with a built-in delay-locked loop. - Sung-Rung Han; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2005)

CMOS wideband amplifiers using multiple inductive-series peaking technique. - Chia-Hsin Wu; Chih-Hun Lee; Wei-Sheng Chen; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2005)

CMOS current-mode divider and its applications. - Weihsing Liu; Shen-Iuan Liu; Shui-Ken Wei (IEEE Trans. Circuits Syst. II Express Briefs, 2005)

Selective metal parallel shunting inductor and its VCO application. - Chia-Hsin Wu; Chun-Yi Kuo; Shen-Iuan Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

A 44GHz Dual-Modulus Divide-by-4/5 Prescaler in 90nm CMOS Technology. - Chihun Lee; Lan-chou Cho; Shen-Iuan Liu (CICC, 2006)

A 10Gbps Burst-Mode CDR Circuit in 0.18μm CMOS. - Che-Fu Liang; Sy-Chyuan Hwu; Shen-Iuan Liu (CICC, 2006)

A 14-band Frequency Synthesizer for MB-OFDM UWB Application. - Che-Fu Liang; Shen-Iuan Liu; Yen-Horng Chen; Tzu-Yi Yang; Gin-Kou Ma (ISSCC, 2006)

A 10Gb/s CMOS AGC Amplifier with 35dB Dynamic Range for 10Gb Ethernet. - Chih-Fan Liao; Shen-Iuan Liu (ISSCC, 2006)

A 1 V Phase Locked Loop with Leakage Compensation in 0.13 µm CMOS Technology. - Chi-Nan Chuang; Shen-Iuan Liu (IEICE Trans. Electron., 2006)

All-Digital Clock Deskew Buffer with Variable Duty Cycles. - Shao-Ku Kao; Shen-Iuan Liu (IEICE Trans. Electron., 2006)

A 0.7-2-GHz self-calibrated multiphase delay-locked loop. - Hsiang-Hui Chang; Jung-Yu Chang; Chun-Yi Kuo; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2006)

A Calibrated Pulse Generator for Impulse-Radio UWB Applications. - Che-Fu Liang; Shih-Tsai Liu; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2006)

All-digital delay-locked loop/pulsewidth-control loop with adjustable duty cycles. - You-Jen Wang; Shao-Ku Kao; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2006)

A 155.52 mbps-3.125 gbps continuous-rate clock and data recovery circuit. - Rong-Jyi Yang; Kuan-Hua Chao; Sy-Chyuan Hwu; Chuan-Kang Liang; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2006)

All-Digital Fast-Locked Synchronous Duty-Cycle Corrector. - Shao-Ku Kao; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

A spur-reduction technique for a 5-GHz frequency synthesizer. - Chun-Yi Kuo; Jung-Yu Chang; Shen-Iuan Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

A 200-Mbps∼2-Gbps continuous-rate clock-and-data-recovery circuit. - Rong-Jyi Yang; Kuan-Hua Chao; Shen-Iuan Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

A 2.4GHz Efficiency-Enhanced Rectifier for Wireless Telemetry. - Ke-Hou Chen; Jian-Hao Lu; Shen-Iuan Liu (CICC, 2007)

A 33.6-to-33.8Gb/s Burst-Mode CDR in 90nm CMOS. - Lan-Chou Cho; Chihun Lee; Shen-Iuan Liu (ISSCC, 2007)

A 40GHz DLL-Based Clock Generator in 90nm CMOS Technology. - Chi-Nan Chuang; Shen-Iuan Liu (ISSCC, 2007)

A 58-to-60.4GHz Frequency Synthesizer in 90nm CMOS. - Chihun Lee; Shen-Iuan Liu (ISSCC, 2007)

A 40Gb/s Transimpedance-AGC Amplifier with 19dB DR in 90nm CMOS. - Chih-Fan Liao; Shen-Iuan Liu (ISSCC, 2007)

A 10-BIT 100MS/s pipelined ADC IN 0.18μm CMOS technology. - Hwei-Yu Lee; Shen-Iuan Liu (SoCC, 2007)

A 7-BIT 400MS/s sub-ranging flash ADC in 0.18um CMOS. - Hwei-Yu Lee; I-Hsin Wang; Shen-Iuan Liu (SoCC, 2007)

A Multi-Band Burst-Mode Clock and Data Recovery Circuit. - Che-Fu Liang; Sy-Chyuan Hwu; Shen-Iuan Liu (IEICE Trans. Electron., 2007)

A 1.2-V 37-38.5-GHz Eight-Phase Clock Generator in 0.13-µm CMOS Technology. - Lan-Chou Cho; Chihun Lee; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2007)

A Broadband Noise-Canceling CMOS LNA for 3.1-10.6-GHz UWB Receivers. - Chih-Fan Liao; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2007)

A 40-550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR Algorithm. - Rong-Jyi Yang; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2007)

A 2.5 GHz All-Digital Delay-Locked Loop in 0.13 µm CMOS Technology. - Rong-Jyi Yang; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2007)

A DLL-Based Variable-Phase Clock Buffer. - Chao-Chyun Chen; Jung-Yu Chang; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

An Ultra-Wide-Band 0.4-10-GHz LNA in 0.18-μm CMOS. - Ke-Hou Chen; Jian-Hao Lu; Bo-Jiun Chen; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

A 0.5-5-GHz Wide-Range Multiphase DLL With a Calibrated Charge Pump. - Chi-Nan Chuang; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

A Time-Constant Calibrated Phase-Locked Loop With a Fast-Locked Time. - Sung-Rung Han; Chi-Nan Chuang; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

A 62.5-625-MHz Anti-Reset All-Digital Delay-Locked Loop. - Shao-Ku Kao; Bo-Jiun Chen; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

Spur-Suppression Techniques for Frequency Synthesizers. - Che-Fu Liang; Hsin-Hua Chen; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

A Low-Jitter Spread Spectrum Clock Generator Using FDMP. - Ding-Shiuan Shen; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

A 20/10/5/2.5Gb/s Power-scaling Burst-Mode CDR Circuit Using GVCO/Div2/DFF Tri-mode Cells. - Che-Fu Liang; Shen-Iuan Liu (ISSCC, 2008)

A 40Gb/s CMOS Serial-Link Receiver with Adaptive Equalization and CDR. - Chih-Fan Liao; Shen-Iuan Liu (ISSCC, 2008)

3.5mW W-Band Frequency Divider with Wide Locking Range in 90nm CMOS Technology. - Kun-Hung Tsai; Lan-Chou Cho; Jia-Hao Wu; Shen-Iuan Liu (ISSCC, 2008)

Capacitor-free low dropout regulators using nested Miller compensation with active resistor and 1-bit programmable capacitor array. - Wei-Jen Huang; Shen-Iuan Liu (IET Circuits Devices Syst., 2008)

An Infinite Phase Shift Delay-Locked Loop With Voltage-Controlled Sawtooth Delay Line. - Chao-Chyun Chen; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2008)

A Digital Calibration Technique for Charge Pumps in Phase-Locked Systems. - Che-Fu Liang; Shin-Hua Chen; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2008)

A Jitter-Tolerance-Enhanced CDR Using a GDCO-Based Phase Detector. - Che-Fu Liang; Sy-Chyuan Hwu; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2008)

40 Gb/s Transimpedance-AGC Amplifier and CDR Circuit for Broadband Data Receivers in 90 nm CMOS. - Chih-Fan Liao; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2008)

A 40 Gb/s CMOS Serial-Link Receiver With Adaptive Equalization and Clock/Data Recovery. - Chih-Fan Liao; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2008)

Introduction to the Special Issue on the 2008 IEEE International Solid-State Circuits Conference. - Sanroku Tsukamoto; Shen-Iuan Liu; Stefan Heinen; Roland Thewes; Jri Lee (IEEE J. Solid State Circuits, 2008)

A 3-8 GHz Delay-Locked Loop With Cycle Jitter Calibration. - Chi-Nan Chuang; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

A Delay-Locked Loop With Statistical Background Calibration. - Shao-Ku Kao; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

A 50.8-53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13- mum CMOS. - Chihun Lee; Lan-Chou Cho; Jia-Hao Wu; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

10-Gb/s Inductorless CDRs With Digital Frequency Calibration. - Che-Fu Liang; Hong-Lin Chu; Shen-Iuan Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

An All-Digital Fast-Locking Programmable DLL-Based Clock Generator. - Chuan-Kang Liang; Rong-Jyi Yang; Shen-Iuan Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

Full-Rate Bang-Bang Phase/Frequency Detectors for Unilateral Continuous-Rate CDRs. - Shao-Hung Lin; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

A 0.18-muhbox m CMOS 1.25-Gbps Automatic-Gain-Control Amplifier. - I-Hsin Wang; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

A 140MS/s 10-bit Pipelined ADC with a Folded S/H Stage. - Hwei-Yu Lee; Shen-Iuan Liu (ISCAS, 2009)

A leakage-suppression technique for phase-locked systems in 65nm CMOS. - Chao-Ching Hung; Shen-Iuan Liu (ISSCC, 2009)

A 128.24-to-137.00GHz injection-locked frequency divider in 65nm CMOS. - Bo-Yu Lin; Kun-Hung Tsai; Shen-Iuan Liu (ISSCC, 2009)

A 43.7mW 96GHz PLL in 65nm CMOS. - Kun-Hung Tsai; Shen-Iuan Liu (ISSCC, 2009)

A 1.5 GHz phase-locked loop with leakage current suppression in 65 nm CMOS. - Jung-Yu Chang; Shen-Iuan Liu (IET Circuits Devices Syst., 2009)

A 33.6-to-33.8 Gb/s Burst-Mode CDR in 90 nm CMOS Technology. - Lan-Chou Cho; Chihun Lee; Chao-Ching Hung; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2009)

A 1.5 GHz All-Digital Spread-Spectrum Clock Generator. - Sheng-You Lin; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2009)

A Single-PLL UWB Frequency Synthesizer Using Multiphase Coupled Ring Oscillator and Current-Reused Multiplier. - Jung-Yu Chang; Che-Wei Fan; Che-Fu Liang; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

A 20-MHz to 3-GHz Wide-Range Multiphase Delay-Locked Loop. - Chi-Nan Chuang; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

A Fully Differential Comparator-Based Switched-Capacitor DeltaSigma Modulator. - Mu-Chen Huang; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

A Leakage-Compensated PLL in 65-nm CMOS Technology. - Chao-Ching Hung; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

A 104- to 112.8-GHz CMOS Injection-Locked Frequency Divider. - I-Ting Lee; Kun-Hung Tsai; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

A Phase-Locked Loop With Self-Calibrated Charge Pumps in 3- muhboxm LTPS-TFT Technology. - Wei-Ming Lin; Shen-Iuan Liu; Chun-Hung Kuo; Chun-Huai Li; Yao-Jen Hsieh; Chun-Ting Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

A 10-Gb/s Inductorless CMOS Analog Equalizer With an Interleaved Active Feedback Topology. - Jian-Hao Lu; Ke-Hou Chen; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Comments on "A 10-Gb/s Inductorless CMOS Analog Equalizer With an Interleaved Active Feedback Topology". - Jian-Hao Lu; Ke-Hou Chen; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

A 50-Gb/s 10-mW Analog Equalizer Using Transformer Feedback Technique in 65-nm CMOS Technology. - Jian-Hao Lu; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

An 8-bit 20-MS/s ZCBC Time-Domain Analog-to-Digital Data Converter. - I-Hsin Wang; Hwei-Yu Lee; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

A Merged CMOS Digital Near-End Crosstalk Canceller and Analog Equalizer for Multi-Lane Serial-Link Receivers. - Jian-Hao Lu; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2010)

A Phase-Locked Loop With Background Leakage Current Compensation. - Jung-Yu Chang; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A 10-MS/s-to-100-kS/s Power-Scalable Fully Differential CBSC 10-Bit Pipelined ADC With Adaptive Biasing. - Mu-Chen Huang; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A 1.62/2.7-Gb/s Adaptive Transmitter With Two-Tap Preemphasis Using a Propagation-Time Detector. - Shih-Yuan Kao; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A 20-Gb/s Transmitter With Adaptive Preemphasis in 65-nm CMOS Technology. - Shih-Yuan Kao; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A leakage-current-recycling phase-locked loop in 65nm CMOS technology. - I-Ting Lee; Yun-Ta Tsai; Shen-Iuan Liu (A-SSCC, 2011)

3.6mW D-band divide-by-3 injection-locked frequency dividers in 65nm CMOS. - I-Ting Lee; Chiao-Hsing Wang; Shen-Iuan Liu (A-SSCC, 2011)

A 6Gb/s receiver with 32.7dB adaptive DFE-IIR equalization. - Yi-Chieh Huang; Shen-Iuan Liu (ISSCC, 2011)

A 20Gb/s digitally adaptive equalizer/DFE with blind sampling. - Yu-Ming Ying; Shen-Iuan Liu (ISSCC, 2011)

Analysis and Design of D-Band Injection-Locked Frequency Dividers. - Bo-Yu Lin; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2011)

A 1-16-Gb/s Wide-Range Clock/Data Recovery Circuit With a Bidirectional Frequency Detector. - Chang-Lin Hsieh; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

Decision Feedback Equalizers Using the Back-Gate Feedback Technique. - Chang-Lin Hsieh; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A Rail-to-Rail Class-B Buffer With DC Level-Shifting Current Mirror and Distributed Miller Compensation for LCD Column Drivers. - Wei-Jen Huang; Shigeisa Nagayasu; Shen-Iuan Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

A Noise Filtering Technique for Fractional-N Frequency Synthesizers. - Chao-Ching Hung; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A 40-GHz Fast-Locked All-Digital Phase-Locked Loop Using a Modified Bang-Bang Algorithm. - Chao-Ching Hung; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A 132.6-GHz Phase-Locked Loop in 65 nm Digital CMOS. - Bo-Yu Lin; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A Digitally-Calibrated Phase-Locked Loop With Supply Sensitivity Suppression. - Shih-Yuan Kao; Shen-Iuan Liu (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A 6.7MHz-to-1.24GHz 0.0318mm2 fast-locking all-digital DLL in 90nm CMOS. - Min-Han Hsieh; Liang-Hsin Chen; Shen-Iuan Liu; Charlie Chung-Ping Chen (ISSCC, 2012)

A 2.4GHz sub-harmonically injection-locked PLL with self-calibrated injection timing. - Yi-Chieh Huang; Shen-Iuan Liu (ISSCC, 2012)

A fast-locking phase-locked loop using CP control and gated VCO. - I-Ting Lee; Yun-Ta Tsai; Shen-Iuan Liu (VLSI-DAT, 2012)

A Leakage-Current-Recycling Phase-Locked Loop in 65 nm CMOS Technology. - I-Ting Lee; Yun-Ta Tsai; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2012)

Introduction to the Special Section on the 2011 Asian Solid-State Circuits Conference (A-SSCC). - Shen-Iuan Liu; Tsung-Hsien Lin; Woogeun Rhee (IEEE J. Solid State Circuits, 2012)

Inductorless Wideband CMOS Low-Noise Amplifiers Using Noise-Canceling Technique. - Ke-Hou Chen; Shen-Iuan Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

An All-Digital Jitter Tolerance Measurement Technique for CDR Circuits. - Yi-Chieh Huang; Ping-Ying Wang; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

G-Band Injection-Locked Frequency Dividers Using π-type LC Networks. - I-Ting Lee; Shen-Iuan Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A 6-GHz All-Digital Fractional-N Frequency Synthesizer Using FIR-Embedded Noise Filtering Technique. - I-Ting Lee; Hung-Yu Lu; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A 104-GHz Phase-Locked Loop Using a VCO at Second Pole Frequency. - Kun-Hung Tsai; Shen-Iuan Liu (IEEE Trans. Very Large Scale Integr. Syst., 2012)

A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing. - I-Ting Lee; Yen-Jen Chen; Shen-Iuan Liu; Chewnpu Jou; Fu-Lung Hsueh; Hsieh-Hung Hsieh (ISSCC, 2013)

Ultrasonic telemetry and neural stimulator with FSK-PWM signaling. - Ye-Sing Luo; Jiun-Ru Wang; Wei-Jen Huang; Je-Yu Tsai; I-Chin Wu; Yi-Fang Liao; Wan-Ting Tseng; Chen-Tung Yen; Pai-Chi Li; Shen-Iuan Liu (VLSI-DAT, 2013)

Divide-by-Three Injection-Locked Frequency Dividers Over 200 GHz in 40-nm CMOS. - Pin-Hao Feng; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2013)

A 2.4-GHz Subharmonically Injection-Locked PLL With Self-Calibrated Injection Timing. - Yi-Chieh Huang; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2013)

A 7.5-Gb/s One-Tap-FFE Transmitter With Adaptive Far-End Crosstalk Cancellation Using Duty Cycle Detection. - Shih-Yuan Kao; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2013)

A 10-Gb/s Adaptive Parallel Receiver With Joint XTC and DFE Using Power Detection. - Shih-Yuan Kao; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2013)

A Submicrowatt 1.1-MHz CMOS Relaxation Oscillator With Temperature Compensation. - Yu-Hsuan Chiang; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

An All-Digital Spread-Spectrum Clock Generator With Self-Calibrated Bandwidth. - I-Ting Lee; Shih-Han Ku; Shen-Iuan Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A 4.8-GHz Dividerless Subharmonically Injection-Locked All-Digital PLL With a FOM of -252.5 dB. - I-Ting Lee; Kai-Hui Zeng; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

4-Gb/s Parallel Receivers With Adaptive Far-End Crosstalk Cancellation. - Yan-Yu Lin; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

4-Gb/s Parallel Receivers With Adaptive FEXT Cancellation by Pulse Width and Amplitude Calibrations. - Yan-Yu Lin; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

Ultrasonic Power/Data Telemetry and Neural Stimulator With OOK-PM Signaling. - Ye-Sing Luo; Jiun-Ru Wang; Wei-Jen Huang; Je-Yu Tsai; Yi-Fang Liao; Wan-Ting Tseng; Chen-Tung Yen; Pai-Chi Li; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A Wide-Range PLL Using Self-Healing Prescaler/VCO in 65-nm CMOS. - I-Ting Lee; Yun-Ta Tsai; Shen-Iuan Liu (IEEE Trans. Very Large Scale Integr. Syst., 2013)

A 0.3V 10bit 7.3fJ/conversion-step SAR ADC in 0.18μm CMOS. - Cheng-En Hsieh; Shen-Iuan Liu (A-SSCC, 2014)

A 2×25 Gb/s clock and data recovery with background amplitude-locked loop. - Chien-Kai Kao; Kuan-Lin Fu; Shen-Iuan Liu (A-SSCC, 2014)

A 0.43pJ/bit true random number generator. - Ting-Kuei Kuan; Yu-Hsuan Chiang; Shen-Iuan Liu (A-SSCC, 2014)

A 5-20 Gb/s power scalable adaptive linear equalizer using edge counting. - Yuan-Fu Lin; Chang-Cheng Huang; Jiunn-Yih Max Lee; Chih-Tien Chang; Shen-Iuan Liu (A-SSCC, 2014)

A low-input-swing AC-DC voltage multiplier using Schottky diodes. - Ye-Sing Luo; Shen-Iuan Liu (A-SSCC, 2014)

A silicon nanowire-based bio-sensing system with digitized outputs for acute myocardial infraction diagnosis. - Shih-Hsiang Shen; Chung-Yi Ting; Chi-Yun Liu; Hua Cheng; Shen-Iuan Liu; Chih-Ting Lin (BHI, 2014)

Nanopower CMOS Relaxation Oscillators With Sub-100 ppm°C Temperature Coefficient. - Yu-Hsuan Chiang; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A 3-25 Gb/s Four-Channel Receiver With Noise-Canceling TIA and Power-Scalable LA. - Yu-Hsun Chien; Kuan-Lin Fu; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

An All-Digital Despreading Clock Generator. - I-Ting Lee; Shih-Han Ku; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A digital bang-bang phase-locked loop with bandwidth calibration. - Chi-Huan Chiang; Chang-Cheng Huang; Shen-Iuan Liu (A-SSCC, 2015)

A digital bang-bang phase-locked loop with automatic loop gain control and loop latency reduction. - Ting-Kuei Kuan; Shen-Iuan Liu (VLSIC, 2015)

A Loop Gain Optimization Technique for Integer-N TDC-Based Phase-Locked Loops. - Ting-Kuei Kuan; Shen-Iuan Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A Subharmonically Injection-Locked PLL With Calibrated Injection Pulsewidth. - Chih-Lu Wei; Ting-Kuei Kuan; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A Subharmonically Injection-Locked All-Digital PLL Without Main Divider. - Kai-Hui Zeng; Ting-Kuei Kuan; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A digital MDLL using switched biasing technique to reduce low-frequency phase noise. - Chi-Huan Chiang; Chang-Cheng Huang; Ting-Kuei Kuan; Shen-Iuan Liu (A-SSCC, 2016)

19.5 A 3.2GHz digital phase-locked loop with background supply-noise cancellation. - Che-Wei Yeh; Cheng-En Hsieh; Shen-Iuan Liu (ISSCC, 2016)

A 6.7 MHz to 1.24 GHz 0.0318 mm 2 Fast-Locking All-Digital DLL Using Phase-Tracing Delay Unit in 90 nm CMOS. - Min-Han Hsieh; Liang-Hsin Chen; Shen-Iuan Liu; Charlie Chung-Ping Chen (IEEE J. Solid State Circuits, 2016)

A Bang Bang Phase-Locked Loop Using Automatic Loop Gain Control and Loop Latency Reduction Techniques. - Ting-Kuei Kuan; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2016)

A 10-bit 40-MS/s Time-Domain Two-Step ADC With Short Calibration Time. - Liang-Jen Chen; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A Digital PLL Using Oversampling Delta-Sigma TDC. - Chih-Lu Wei; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A 12-bit 3.4 MS/s Two-Step Cyclic Time-Domain ADC in 0.18-µm CMOS. - Liang-Jen Chen; Shen-Iuan Liu (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A 56Gbps PAM-4 optical receiver front-end. - Kuan-Lin Fu; Shen-Iuan Liu (A-SSCC, 2017)

A Voltage Multiplier With Adaptive Threshold Voltage Compensation. - Ye-Sing Luo; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2017)

A 0.035-pJ/bit/dB 20-Gb/s Adaptive Linear Equalizer With an Adaptation Time of 2.68 µs. - Kuan-Yu Chen; Wei-Yung Chen; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A 0.31-pJ/bit 20-Gb/s DFE With 1 Discrete Tap and 2 IIR Filters Feedback in 40-nm-LP CMOS. - Kuan-Yu Chen; Wei-Yung Chen; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A 5 Gb/s Voltage-Mode Transmitter Using Adaptive Time-Based De-Emphasis. - Wun-Jian Su; Shen-Iuan Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A 2.25-2.7 GHz Area-Efficient Subharmonically Injection-Locked Fractional-N Frequency Synthesizer With a Fast-Converging Correlation Loop. - Yen-Hsiang Tseng; Che-Wei Yeh; Shen-Iuan Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A 13.56 MHz 88.7%-PCE Voltage Doubling Rectifier Using Adaptive Delay Time and Pulse-Width Control. - Ye-Sing Luo; Hsing-Hung Lin; Shen-Iuan Liu (A-SSCC, 2018)

Development of 400 Gb/s optical transceivers for SMF based datacenter optical interconnect. - San-Liang Lee; Jyehong Chen; Shen-Iuan Liu; Chang-Fa Yang; Hen-Wai Tsao; Shih-Hsiang Hsu; Chien-Chung Lin; Chun-Liang Yang; Zhong Jie Zhang; Kuan-Lin Fu; Lung Wei Chung; Tomas Pankra (WOCC, 2018)

A Digital Phase-Locked Loop With Background Supply Voltage Sensitivity Minimization. - Che-Wei Tien; Shen-Iuan Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A Sub-Sampling PLL with Robust Operation under Supply Interference and Short Re-Locking Time. - Yuan Cheng Qian; Yen-Yu Chao; Shen-Iuan Liu (A-SSCC, 2019)

A PVT-Tolerant Injection-Locked Clock Multiplier With a Frequency Calibrator Using a Delay Time Detector. - Che-Wei Tien; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

An On-Chip Relaxation Oscillator With Comparator Delay Compensation. - Yi-An Chang; Trio Adiono; Amy Hamidah; Shen-Iuan Liu (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A 13.4-MHz Relaxation Oscillator With Temperature Compensation. - Yi-An Chang; Shen-Iuan Liu (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A PVT-Tolerant MDLL Using a Frequency Calibrator and a Voltage Monitor. - Yu-Kai Chiu; Shen-Iuan Liu (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A 2.4-GHz Frequency-Drift-Compensated Phase-Locked Loop With 2.43 ppm/°C Temperature Coefficient. - Cheng-En Hsieh; Shen-Iuan Liu (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A 500nW-50μ W Indoor Photovoltaic Energy Harvester with Multi-mode MPPT. - Ming-Chia Chang; Min-Hsuan Wu; Shen-Iuan Liu (VLSI-DAT, 2020)

An Indoor Photovoltaic Energy Harvester Using Time-Based MPPT and On-Chip Photovoltaic Cell. - Ming-Chia Chang; Shen-Iuan Liu (IEEE Trans. Circuits Syst., 2020)

A 13.56 MHz Current-Mode Wireless Power Receiver With Energy-Investment Capability. - Chung-Jen Kuo; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A 1.22 mW 2.4 GHz PLL Using a Single-Ring-Oscillator-Based Integrator With Background Frequency Calibration. - Guan-Yu Su; Shen-Iuan Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

A 2.4-GHz Area-Efficient and Fast-Locking Subharmonically Injection-Locked Type-I PLL. - Ming-Han Chou; Shen-Iuan Liu (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A 64-Gb/s PAM-4 Optical Receiver With Amplitude/Phase Correction and Threshold Voltage/Data Level Calibration. - Kuan-Lin Fu; Shen-Iuan Liu (IEEE Trans. Very Large Scale Integr. Syst., 2020)

An Adaptive Loop Gain Tracking Digital PLL Using Spectrum-Balancing Technique. - Guan-Yu Su; Zhi-Heng Kang; Shen-Iuan Liu (VLSI-DAT, 2021)

A Digital Phase-Locked Loop With Background Supply Noise Cancellation. - Yen-Min Tseng; Yu-Chi Yen; Shen-Iuan Liu (VLSI-DAT, 2021)

A 10.4-16-Gb/s Reference-Less Baud-Rate Digital CDR With One-Tap DFE Using a Wide-Range FD. - Wei-Ming Chen; Yun-Sheng Yao; Shen-Iuan Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 5-Gb/s Adaptive Digital CDR Circuit With SSC Capability and Enhanced High-Frequency Jitter Tolerance. - Shun-Chi Chang; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A Type-I PLL With Foreground Loop Bandwidth Calibration. - Ming-Han Chou; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 2.4-3.0GHz Process-Tolerant Sub-Sampling PLL With Loop Bandwidth Calibration. - Yong-Ru Lu; Shen-Iuan Liu; Yu-Che Yang; Han-Chang Kang; Chih-Lung Chen; Ka-Un Chan; Ying-Hsi Lin (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A Jitter-Tolerance-Enhanced Digital CDR Circuit Using Background Loop Gain Controller. - Yun-Sheng Yao; Chang-Cheng Huang; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

An Adaptive Digital PLL Based on BBPFD Transition Probability. - Zhi-Heng Kang; Yu-Chi Yen; Guan-Yu Su; Shen-Iuan Liu (VLSI-DAT, 2022)

An Injection-Locked Clock Multiplier With Injection Strength Calibration. - Yen-Min Tseng; Yu-Chi Yen; Shen-Iuan Liu (VLSI-DAT, 2022)

A 2-3 GHz Fast-Locking PLL Using Phase Error Compensator. - Jia-Rong Chang; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 20-Gb/s Jitter-Tolerance-Enhanced Digital CDR With One-Tap DFE. - Wei-Ming Chen; Yun-Sheng Yao; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 1.45-pJ/b 16-Gb/s Edge-Based Sub-Baud-Rate Digital CDR Circuit. - Wen-Chi Huang; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Low-Jitter Sub-Sampling PLL With a Sub-Sampling DLL. - Yuan Cheng Qian; Yen-Yu Chao; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Wide-Range FD for Referenceless Baud-Rate CDR Circuits. - Yun-Sheng Yao; Chang-Cheng Huang; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 0.0067-mm2 12-bit 20-MS/s SAR ADC Using Digital Place-and-Route Tools in 40-nm CMOS. - Yao-Hung Tsai; Shen-Iuan Liu (IEEE Trans. Very Large Scale Integr. Syst., 2022)

A 1.6-GHz DPLL Using Feedforward Phase-Error Cancellation. - Zhi-Heng Kang; Shen-Iuan Liu (IEEE J. Solid State Circuits, 2023)

A 0.91-pJ/b 20.8-32-Gb/s Reference-Less Sub-Baud-Rate CDR Circuit. - Yao-Hung Tsai; Wen-Chi Huang; Shen-Iuan Liu (A-SSCC, 2024)

A 16-Gb/s Baud-Rate CDR Circuit With One-Tap Speculative DFE and Wide Frequency Capture Range. - Po-Yuan Chou; Wei-Ming Chen; Shen-Iuan Liu (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A 0.079-pJ/b/dB 32-Gb/s 2× Half-Baud-Rate CDR Circuit With Frequency Detector. - Yi-Hao Lan; Shen-Iuan Liu (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A 12.93-16 Gb/s Reference-Less Baud-Rate CDR Circuit With One-Tap DFE and Semirotational Frequency Detection. - Hsi-Kai Peng; Shen-Iuan Liu (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A 36-Gb/s 2× Half-Baud-Rate Adaptive Receiver in 28-nm CMOS. - Yi-Hao Lan; Shen-Iuan Liu (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A 40-Gb/s PAM-3 Receiver With Modified Summer-Merged Slicers and PRTS Checker. - Jhe-En Lin; Yi-Hao Lan; Shen-Iuan Liu (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A 48-Gb/s Baud-Rate PAM-4 Receiver Using Modified Time-Interpolated Latches. - Yuan-Pang Huang; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 59.6fsrms Jitter Sub-Sampling PLL With Foreground Open-Loop Gain Calibration. - Yu-Chi Yen; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A 0.875-0.95-pJ/b 40-Gb/s PAM-3 Baud-Rate Receiver With One-Tap DFE. - Jhe-En Lin; Shen-Iuan Liu (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A 0.07 pJ/b/dB 36-Gb/s PAM-3 Receiver Using Inductor-Reused CTLE and One-Tap Loop-Unrolled DFE in 22-nm CMOS. - Pin-Yuan Chiu; Shen-Iuan Liu (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)