By using grey system and Neural-Fuzzy Network methods to obtain the threshold voltage of submicron n-MOSFET DUTs. - Shen-Li Chen; Dun-Ying Shu (FSKD, 2015)

Anti-ESD impacts on 60-V P-channel LDMOS devices as none-ODs zone inserting in the bulk region. - Shen-Li Chen; Shawn Chang; Yu-Ting Huang 007; Shun-Bao Chang (ICCE-TW, 2015)

ESD reliability building in 0.25 μm 60-V p-channel LDMOS DUTs with different embedded SCRs. - Shen-Li Chen; Yu-Ting Huang 007; Shawn Chang; Shun-Bao Chang (ICCE-TW, 2015)

The I-V Characteristic Prediction of BCD LV pMOSFET Devices Based on an ANFIS-Based Methodology. - Shen-Li Chen (Adv. Fuzzy Syst., 2015)

ESD protection design for the 45-V pLDMOS-SCR (p-n-p-arranged) devices with source-discrete distributions. - Shen-Li Chen; Yu-Ting Huang 007; Chih-Ying Yen; Kuei-Jyun Chen; Yi-Cih Wu; Jia-Ming Lin; Chih-Hung Yang (GCCE, 2016)

Design on ESD robustness of source-side discrete distribution in the 60-V high-voltage nLDMOS devices. - Shen-Li Chen; Chih-Hung Yang; Chih-Ying Yen; Kuei-Jyun Chen; Yi-Cih Wu; Jia-Ming Lin (ICCE-TW, 2016)

Design of High-ESD Reliability in HV Power pLDMOS Transistors by the Drain-Side Isolated SCRs. - Shen-Li Chen; Yu-Ting Huang 007; Yi-Cih Wu (IEICE Trans. Electron., 2017)

Design and Impact on ESD/LU Immunities by Drain-Side Super-Junction Structures in Low-(High-)Voltage MOSFETs for the Power Applications. - Shen-Li Chen; Yu-Ting Huang 007; Shawn Chang (IEICE Trans. Electron., 2018)

Sensing and Reliability Improvement of Electrostatic-Discharge Transient by Discrete Engineering for High-Voltage 60-V n-Channel Lateral-Diffused MOSFETs with Embedded Silicon-Controlled Rectifiers. - Shen-Li Chen; Yi-Cih Wu (Sensors, 2018)

ESD Immunity Impacts of the Drain-Side Heterojunction Device Addition in HV 60 V n/pLDMOS Devices. - Sheng-Kai Fan; Shen-Li Chen; Yu-Lin Jhou; Pei-Lin Wu; Po-Lin Lin (GCCE, 2019)

Evaluating the Drift-Region Length Effect of nLDMOS on ESD Ability with a TLP Testing System. - Po-Lin Lin; Shen-Li Chen; Pei-Lin Wu; Yu-Lin Jhou; Sheng-Kai Fan (GCCE, 2019)

Channel- & Drift Region's STI-Lengths Impacts of ESD Immunity in HV 60 V nLDMOS Devices. - Sheng-Kai Fan; Shen-Li Chen; Yu-Lin Jhou; Pei-Lin Wu; Po-Lin Lin (ICCE-TW, 2019)

ESD-Reliability Investigation 1of an UHV Elliptical LDMOS-SCR by the Drain-Side Junction Replacement. - Po-Lin Lin; Shen-Li Chen; Pei-Lin Wu; Yu-Lin Jhou; Sheng-Kai Fan (ICCE-TW, 2019)

A Novel SCR-based Schottky Diode and Lightly P-well Additions of HV 60V nLDMOS on ESD Capability. - Sheng-Kai Fan; Shen-Li Chen; Po-Lin Lin; Shi-Zhe Hong; Tien-Yu Lan; Yu-Jie Zhou (ICCE-TW, 2020)

ESD-capability Influences of UHV Circular nLDMOS Transistors by the Drain-side Ladder-step STI. - Tien-Yu Lan; Shen-Li Chen; Sheng-Kai Fan; Po-Lin Lin; Yu-Jie Zhou; Shi-Zhe Hong; Hung-Wei Chen (ICCE-TW, 2020)

Improving the ESD Robustness of an Ultra-high Voltage nLDMOS Device with the Embedded Schottky Diode. - Po-Lin Lin; Shen-Li Chen; Sheng-Kai Fan; Tien-Yu Lan; Yu-Jie Zhou; Shi-Zhe Hong (ICCE-TW, 2020)

Strengthened ESD Reliability of HV nLDMOSs with Embedded Horizontal Schottky Devices. - Shi-Zhe Hong; Shen-Li Chen; Sheng-Kai Fan; Po-Lin Lin; Tien-Yu Lan; Yu-Jie Zhou (ICKII, 2020)

ESD-ability of Circular nLDMOS Transistors of UHV by Super-junction Length Modulation and Concentration Gradient. - Tien-Yu Lan; Shen-Li Chen; Po-Lin Lin; Sheng-Kai Fan; Yu-Jie Zhou; Shi-Zhe Hong; Hung-Wei Chen (ICKII, 2020)

ESD-capability Enhancement of Ultra-high Voltage nLDMOSs by the DPW Discrete Layer. - Yu-Jie Zhou; Shen-Li Chen; Pei-Lin Wu; Po-Lin Lin; Sheng-Kai Fan; Tien-Yu Lan; Shi-Zhe Hong (ICKII, 2020)

ESD-Immunity Impact of HV pLDMOS with Drain-side Embedded Horizontal P-type Schottky Modulations. - Shi-Zhe Hong; Shen-Li Chen; Tien-Yu Lan; Yu-Jie Zhou; Zhi-Wei Liu; Jhong-Yi Lai (ICCE-TW, 2021)

Holding-voltage Improvement of UHV Circular nLDMOS Transistors by the Drain-side SCR Engineering. - Tien-Yu Lan; Shen-Li Chen; Yu-Jie Zhou; Shi-Zhe Hong; Jhong-Yi Lai; Zhi-Wei Liu (ICCE-TW, 2021)

Improved UHV IGBT-Cell for ESD Protection with High Holding Voltage via a 0.5µm BCD Process. - Yu-Jie Zhou; Shen-Li Chen; Tien-Yu Lan; Shi-Zhe Hong; Zhi-Wei Liu; Zhong-Yi Lai (ICCE-TW, 2021)

ESD Capability Analysis of High-voltage nLDMOSs by the Bulk Terminal Modulation. - Jhong-Yi Lai; Shen-Li Chen; Zhi-Wei Liu; Xing-Chen Mai; Yu-Jie Chung (ICCE-TW, 2022)

An Investigation of ESD-Enhancement by the Drain-side Embedded SCR Area Modulation for HV pLDMOSs. - Zhi-Wei Liu; Shen-Li Chen; Jhong-Yi Lai; Xing-Chen Mai; Yu-Jie Chung (ICCE-TW, 2022)

High-voltage nLDMOS Drain Side Schottky/SCR Modulations for Enhancement Reliability Capabilities. - Ting-En Lin; Shen-Li Chen; Zhi-Wei Liu; Xing-Chen Mai; Xiu-Yuan Yang; Yu-Jie Chung (ICCE-Taiwan, 2023)

ESD-capability Study of High-voltage nLDMOSs with out the Drift Region DPW Effect. - Xiu-Yuan Yang; Xing-Chen Mai; Shen-Li Chen; Yu-Jie Chung; Jhong-Yi Lai; Ting-En Lin (ICCE-Taiwan, 2023)

Latchup-reliability Impact of High-Voltage nLDMOSs with the Parasitic Schottky Area Modulation in the Source Side. - Ting-En Lin; Shen-Li Chen; Xiu-Yuan Yang; Hung-Wei Chen; Yi-Mu Lee (ICCE-Taiwan, 2024)

ESD/Latch-up Immunities Enhancements of HV NLDMOSs by the Embedded Discrete SCR/Schottky Alternating Arrangement Design at the Drain Side. - Xiu-Yuan Yang; Shen-Li Chen; Ting-En Lin; Hung-Wei Chen; Yi-Mu Lee (ICCE-Taiwan, 2024)