Timing driven placement. - Malgorzata Marek-Sadowska; Shen Lin 001 (ICCAD, 1989)

Delay and Area Optimization in Standard-Cell Design. - Shen Lin 001; Malgorzata Marek-Sadowska; Ernest S. Kuh (DAC, 1990)

A fast and efficient algorithm for determining fanout trees in large networks. - Shen Lin 001; Malgorzata Marek-Sadowska (EURO-DAC, 1991)

SWEC: a Step Wise Equivalent Conductance timing simulator for CMOS VLSI circuits. - Shen Lin 001; Malgorzata Marek-Sadowska; Ernest S. Kuh (EURO-DAC, 1991)

Transient Simulation of Lossy Interconnect. - Shen Lin 001; Ernest S. Kuh (DAC, 1992)

Transient simulation of lossy coupled transmission lines. - Shen Lin 001; Ernest S. Kuh (EURO-DAC, 1992)

A New Accurate and Efficient Timing Simulator. - Shen Lin 001; Ernest S. Kuh; Malgorzata Marek-Sadowska (VLSI Design, 1992)

Circuit simulation for large interconnected IC networks. - Shen Lin 001; Ernest S. Kuh (VLSI, 1993)

Stepwise equivalent conductance circuit simulation technique. - Shen Lin 001; Ernest S. Kuh; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Techniques for fast circuit simulation applied to power estimation of CMOS circuits. - Premal Buch; Shen Lin 001; Vijay Nagasamy; Ernest S. Kuh (ISLPD, 1995)