OAL: An obstacle-aware legalization in standard cell placement with displacement minimization. - Sheng Chou; Tsung-Yi Ho (SoCC, 2009)

Routability-driven analytical placement for mixed-size circuit designs. - Meng-Kai Hsu; Sheng Chou; Tzu-Hen Lin; Yao-Wen Chang (ICCAD, 2011)

An Effective and Efficient Framework for Clock Latency Range Aware Clock Network Synthesis. - Sheng Chou; Cheng-Shen Han; Po-Kai Huang; Ko-Fan Tien; Tsung-Yi Ho (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Structure-aware placement for datapath-intensive circuit designs. - Sheng Chou; Meng-Kai Hsu; Yao-Wen Chang (DAC, 2012)

NTUplace4h: A Novel Routability-Driven Placement Algorithm for Hierarchical Mixed-Size Circuit Designs. - Meng-Kai Hsu; Yi-Fang Chen; Chau-Chin Huang; Sheng Chou; Tzu-Hen Lin; Tung-Chieh Chen; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)