A Cost Effective Output Response Analyzer for sum - delta Modulation Based BIST Systems. - Hao-Chiao Hong; Sheng-Chuan Liang (ATS, 2006)

A Cost Effective BIST Second-Order Sigma-Delta-Modulator. - Hao-Chiao Hong; Sheng-Chuan Liang; Hong-Chin Song (DDECS, 2008)

A Low-Cost Output Response Analyzer for the Built-in-Self-Test S-? Modulator Based on the Controlled Sine Wave Fitting Method. - Shao-Feng Hung; Hao-Chiao Hong; Sheng-Chuan Liang (Asian Test Symposium, 2009)

A Built-in-Self-Test Sigma-Delta ADC Prototype. - Hao-Chiao Hong; Sheng-Chuan Liang; Hong-Chin Song (J. Electron. Test., 2009)

A Decorrelating Design-for-Digital-Testability Scheme for Sigma-Delta Modulators. - Hao-Chiao Hong; Sheng-Chuan Liang (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

A Digitally Testable Sigma -Delta Modulator Using the Decorrelating Design-for-Digital-Testability. - Sheng-Chuan Liang; Hao-Chiao Hong (IEEE Trans. Very Large Scale Integr. Syst., 2011)