Optimization of dynamic power consumption in multi-tier gate-level monolithic 3D ICs. - Sheng-En David Lin; Partha Pratim Pande; Dae Hyun Kim 004 (ISQED, 2016)

Construction of All Rectilinear Steiner Minimum Trees on the Hanan Grid. - Sheng-En David Lin; Dae Hyun Kim 004 (ISPD, 2018)

Detailed-Placement-Enabled Dynamic Power Optimization of Multitier Gate-Level Monolithic 3-D ICs. - Sheng-En David Lin; Dae Hyun Kim 004 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Construction of All Multilayer Monolithic Rectilinear Steiner Minimum Trees on the 3D Hanan Grid for Monolithic 3D IC Routing. - Sheng-En David Lin; Dae Hyun Kim 004 (ISPD, 2019)

Routing Complexity Minimization of Monolithic Three-Dimensional Integrated Circuits. - Sheng-En David Lin; Dae Hyun Kim 004 (ISQED, 2019)

Wire Length Characteristics of Multi-Tier Gate-Level Monolithic 3D ICs. - Sheng-En David Lin; Dae Hyun Kim 004 (IEEE Trans. Emerg. Top. Comput., 2019)

Construction of All Rectilinear Steiner Minimum Trees on the Hanan Grid and Its Applications to VLSI Design. - Sheng-En David Lin; Dae Hyun Kim 004 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Construction of All Multilayer Monolithic RSMTs and Its Application to Monolithic 3D IC Routing. - Monzurul Islam Dewan; Sheng-En David Lin; Dae Hyun Kim 004 (ACM Trans. Design Autom. Electr. Syst., 2024)