Voltage-aware chip-level design for reliability-driven pin-constrained EWOD chips. - Sheng-Han Yeh; Jia-Wen Chang; Tsung-Wei Huang; Tsung-Yi Ho (ICCAD, 2012)

Integrated Fluidic-Chip Co-Design Methodology for Digital Microfluidic Biochips. - Jia-Wen Chang; Sheng-Han Yeh; Tsung-Wei Huang; Tsung-Yi Ho (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

An ILP-Based Routing Algorithm for Pin-Constrained EWOD Chips With Obstacle Avoidance. - Jia-Wen Chang; Sheng-Han Yeh; Tsung-Wei Huang; Tsung-Yi Ho (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Voltage-Aware Chip-Level Design for Reliability-Driven Pin-Constrained EWOD Chips. - Sheng-Han Yeh; Jia-Wen Chang; Tsung-Wei Huang; Shang-Tsung Yu; Tsung-Yi Ho (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Reliability-Driven Chip-Level Design for High-Frequency Digital Microfluidic Biochips. - Shang-Tsung Yu; Sheng-Han Yeh; Tsung-Yi Ho (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)