A 1.2V 2MHz BW 0.084mm2 CT ΔΣ ADC with -97.7dBc THD and 80dB DR using low-latency DEM. - Sheng-Jui Huang; Yung-Yu Lin (ISSCC, 2009)

A 0.13 µm CMOS Quad-Band GSM/GPRS/EDGE RF Transceiver Using a Low-Noise Fractional-N Frequency Synthesizer and Direct-Conversion Architecture. - Pei-Wei Chen; Tser-Yu Lin; Ling-Wei Ke; Rickey Yu; Ming-Da Tsai; Stanley Yeh; Yi-Bin Lee; Bosen Tzeng; Yen-Horng Chen; Sheng-Jui Huang; Yu-Hsin Lin; Guang-Kaai Dehng (IEEE J. Solid State Circuits, 2009)

A 75.1dB SNDR, 80.2dB DR, 4th-order feed-forward continuous-time sigma-delta modulator with hybrid integrator for silicon TV-tuner application. - Chen-Yen Ho; Zwei-Mei Lee; Mu-Chen Huang; Sheng-Jui Huang (A-SSCC, 2011)

A SAW-Less GSM/GPRS/EDGE Receiver Embedded in 65-nm SoC. - Chi-Yao Yu; Ivan Siu-Chuang Lu; Yen-Horng Chen; Lan-chou Cho; Chih-hao Eric Sun; Chih-Chun Tang; Hsiang-Hui Chang; Wen-Chang Lee; Sheng-Jui Huang; Tzung-Han Wu; Chinq-Shiun Chiu; George Chien (IEEE J. Solid State Circuits, 2011)

An iterative re-weighted least squares processor design for deblurring parabolic camera images. - Yu-Hsiang Kao; Sheng-Jui Huang; Yi-Chang Lu (GCCE, 2016)

28.3 A 125MHz-BW 71.9dB-SNDR VCO-based CT ΔΣ ADC with segmented phase-domain ELD compensation in 16nm CMOS. - Sheng-Jui Huang; Nathan Egan; Divya Kesharwani; Frank Opteynde; Michael Ashburn (ISSCC, 2017)

An FPGA-Based Liquid Association Calculator for Genome-Wide Co-Expression Analysis. - Chien-An Wang; Sheng-Jui Huang; Yu-Cheng Li; Yi-Chang Lu (DSP, 2018)

Subpixel-Level-Accurate Algorithm for Removing Double-Layered Reflections from a Single Image. - Shih-Wei Hsieh; Yao-Cheng Yang; Chi-Ming Yeh; Sheng-Jui Huang; Yi-Chang Lu (ICIP, 2018)

A Real Time Video Stabilizer Based on Feature Trajectories and Global Mesh Warping. - Sheng-Jui Huang; Yi-Hsien Lin; Chi-Hung Weng; Yi-Chang Lu (APCCAS, 2021)