A Heterogeneous Lightweight Multithreaded Architecture. - Sheng Li 007; Amit Kashyap; Shannon K. Kuntz; Jay B. Brockman; Peter M. Kogge; Paul L. Springer; Gary Block (IPDPS, 2007)

Design of a mask-programmable memory/multiplier array using G4-FET technology. - Jay B. Brockman; Sheng Li 007; Peter M. Kogge; Amit Kashyap; Mohammad M. Mojarradi (DAC, 2008)

Memory model effects on application performance for a lightweight multithreaded architecture. - Sheng Li 007; Shannon K. Kuntz; Peter M. Kogge; Jay B. Brockman (IPDPS, 2008)

McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures. - Sheng Li 007; Jung Ho Ahn; Richard D. Strong; Jay B. Brockman; Dean M. Tullsen; Norman P. Jouppi (MICRO, 2009)

CACTI-P: Architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques. - Sheng Li 007; Ke Chen 020; Jung Ho Ahn; Jay B. Brockman; Norman P. Jouppi (ICCAD, 2011)

System-level integrated server architectures for scale-out datacenters. - Sheng Li 007; Kevin T. Lim; Paolo Faraboschi; Jichuan Chang; Parthasarathy Ranganathan; Norman P. Jouppi (MICRO, 2011)

System implications of memory reliability in exascale computing. - Sheng Li 007; Ke Chen 020; Ming-yu Hsieh; Naveen Muralimanohar; Chad D. Kersey; Jay B. Brockman; Arun F. Rodrigues; Norman P. Jouppi (SC, 2011)

Lightweight Chip Multi-Threading (LCMT): Maximizing Fine-Grained Parallelism On-Chip. - Sheng Li 007; Shannon K. Kuntz; Jay B. Brockman; Peter M. Kogge (IEEE Trans. Parallel Distributed Syst., 2011)

CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory. - Ke Chen 020; Sheng Li 007; Naveen Muralimanohar; Jung Ho Ahn; Jay B. Brockman; Norman P. Jouppi (DATE, 2012)

MAGE: adaptive granularity and ECC for resilient and power efficient memory systems. - Sheng Li 007; Doe Hyun Yoon; Ke Chen 020; Jishen Zhao; Jung Ho Ahn; Jay B. Brockman; Yuan Xie 001; Norman P. Jouppi (SC, 2012)

McSimA+: A manycore simulator with application-level+ simulation and detailed microarchitecture modeling. - Jung Ho Ahn; Sheng Li 007; Seongil O; Norman P. Jouppi (ISPASS, 2013)

Kiln: closing the performance gap between systems with and without persistence support. - Jishen Zhao; Sheng Li 007; Doe Hyun Yoon; Yuan Xie 001; Norman P. Jouppi (MICRO, 2013)

The McPAT Framework for Multicore and Manycore Architectures: Simultaneously Modeling Power, Area, and Timing. - Sheng Li 007; Jung Ho Ahn; Richard D. Strong; Jay B. Brockman; Dean M. Tullsen; Norman P. Jouppi (ACM Trans. Archit. Code Optim., 2013)

History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM Architectures. - Ke Chen 020; Sheng Li 007; Jung Ho Ahn; Naveen Muralimanohar; Jishen Zhao; Cong Xu 002; Seongil O; Yuan Xie 001; Jay B. Brockman; Norman P. Jouppi (ICS, 2015)

Architecting to achieve a billion requests per second throughput on a single key-value store server platform. - Sheng Li 007; Hyeontaek Lim; Victor W. Lee; Jung Ho Ahn; Anuj Kalia; Michael Kaminsky; David G. Andersen; Seongil O; Sukhan Lee 002; Pradeep Dubey (ISCA, 2015)

Buri: Scaling Big-Memory Computing with Hardware-Based Memory Expansion. - Jishen Zhao; Sheng Li 007; Jichuan Chang; John L. Byrne; Laura L. Ramirez; Kevin T. Lim; Yuan Xie 001; Paolo Faraboschi (ACM Trans. Archit. Code Optim., 2015)

Large Pages on Steroids: Small Ideas to Accelerate Big Memory Applications. - Daejin Jung; Sheng Li 007; Jung Ho Ahn (IEEE Comput. Archit. Lett., 2016)

Parallelizing Word2Vec in Multi-Core and Many-Core Architectures. - Shihao Ji 001; Nadathur Satish; Sheng Li 007; Pradeep Dubey (CoRR, 2016)

Achieving One Billion Key-Value Requests per Second on a Single Server. - Sheng Li 007; Hyeontaek Lim; Victor W. Lee; Jung Ho Ahn; Anuj Kalia; Michael Kaminsky; David G. Andersen; Seongil O; Sukhan Lee 002; Pradeep Dubey (IEEE Micro, 2016)

Full-Stack Architecting to Achieve a Billion-Requests-Per-Second Throughput on a Single Key-Value Store Server Platform. - Sheng Li 007; Hyeontaek Lim; Victor W. Lee; Jung Ho Ahn; Anuj Kalia; Michael Kaminsky; David G. Andersen; Seongil O; Sukhan Lee 002; Pradeep Dubey (ACM Trans. Comput. Syst., 2016)

Work as a team or individual: Characterizing the system-level impacts of main memory partitioning. - Eojin Lee; Jongwook Chung; Daejin Jung; Sukhan Lee 002; Sheng Li 007; Jung Ho Ahn (IISWC, 2017)

Parallelizing Word2Vec in Shared and Distributed Memory. - Shihao Ji 001; Nadathur Satish; Sheng Li 007; Pradeep Dubey (IEEE Trans. Parallel Distributed Syst., 2019)

Google's Training Chips Revealed: TPUv2 and TPUv3. - Thomas Norrie; Nishant Patil; Doe Hyun Yoon; George Kurian; Sheng Li 007; James Laudon; Cliff Young; Norman P. Jouppi; David A. Patterson 001 (Hot Chips Symposium, 2020)

A domain-specific supercomputer for training deep neural networks. - Norman P. Jouppi; Doe Hyun Yoon; George Kurian; Sheng Li 007; Nishant Patil; James Laudon; Cliff Young; David A. Patterson 001 (Commun. ACM, 2020)

Searching for Fast Model Families on Datacenter Accelerators. - Sheng Li 007; Mingxing Tan; Ruoming Pang; Andrew Li; Liqun Cheng; Quoc V. Le; Norman P. Jouppi (CVPR, 2021)

NeuroMeter: An Integrated Power, Area, and Timing Modeling Framework for Machine Learning Accelerators Industry Track Paper. - Tianqi Tang 001; Sheng Li 007; Lifeng Nai; Norman P. Jouppi; Yuan Xie 001 (HPCA, 2021)

Ten Lessons From Three Generations Shaped Google's TPUv4i : Industrial Product. - Norman P. Jouppi; Doe Hyun Yoon; Matthew Ashcraft; Mark Gottscho; Thomas B. Jablin; George Kurian; James Laudon; Sheng Li 007; Peter C. Ma; Xiaoyu Ma; Thomas Norrie; Nishant Patil; et al. (ISCA, 2021)

The Design Process for Google's Training Chips: TPUv2 and TPUv3. - Thomas Norrie; Nishant Patil; Doe Hyun Yoon; George Kurian; Sheng Li 007; James Laudon; Cliff Young; Norman P. Jouppi; David A. Patterson 001 (IEEE Micro, 2021)

Hyperscale Hardware Optimized Neural Architecture Search. - Sheng Li 007; Garrett Andersen; Tao Chen 003; Liqun Cheng; Julian Grady; Da Huang; Quoc V. Le; Andrew Li; Xin Li 082; Yang Li 005; Chen Liang; Yifeng Lu; et al. (ASPLOS (3), 2023)

TripLe: Revisiting Pretrained Model Reuse and Progressive Learning for Efficient Vision Transformer Scaling and Searching. - Cheng Fu 002; Hanxian Huang; Zixuan Jiang; Yun Ni; Lifeng Nai; Gang Wu; Liqun Cheng; Yanqi Zhou; Sheng Li 007; Andrew Li; Jishen Zhao (ICCV, 2023)

TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Embeddings. - Norman P. Jouppi; George Kurian; Sheng Li 007; Peter C. Ma; Rahul Nagarajan; Lifeng Nai; Nishant Patil; Suvinay Subramanian; Andy Swing; Brian Towles; Cliff Young; Xiang Zhou; et al. (ISCA, 2023)

Lightwave Fabrics: At-Scale Optical Circuit Switching for Datacenter and Machine Learning Systems. - Hong Liu; Ryohei Urata; Kevin Yasumura; Xiang Zhou; Roy Bannon; Jill Berger; Pedram Dashti; Norm Jouppi; Cedric F. Lam; Sheng Li 007; Erji Mao; Daniel Nelson; et al. (SIGCOMM, 2023)

Experts Weights Averaging: A New General Training Scheme for Vision Transformers. - Yongqi Huang; Peng Ye 006; Xiaoshui Huang; Sheng Li 007; Tao Chen 003; Tong He 001; Wanli Ouyang (CoRR, 2023)

FLIQS: One-Shot Mixed-Precision Floating-Point and Integer Quantization Search. - Jordan Dotzel; Gang Wu; Andrew Li; Muhammad Umar 002; Yun Ni; Mohamed S. Abdelfattah; Zhiru Zhang; Liqun Cheng; Martin G. Dixon; Norman P. Jouppi; Quoc V. Le; Sheng Li 007 (AutoML, 2024)

Learning from Students: Applying t-Distributions to Explore Accurate and Efficient Formats for LLMs. - Jordan Dotzel; Yuzong Chen 001; Bahaa Kotb; Sushma Prasad; Gang Wu; Sheng Li 007; Mohamed S. Abdelfattah; Zhiru Zhang (ICML, 2024)

Reconfigurable Lightwave Fabrics for ML Supercomputers. - Hong Liu; Ryohei Urata; Kevin Yasumura; Xiang Zhou; Roy Bannon; Jill Berger; Pedram Dashti; Norm Jouppi; Cedric F. Lam; Sheng Li 007; Erji Mao; Daniel Nelson; et al. (OFC, 2024)